SN74LS253
Dual 4-Input Multiplexer
with 3-State Outputs
The LSTTL / MSI SN74LS253 is a Dual 4-Input Multiplexer with
3-state outputs. It can select two bits of data from four sources using
common select inputs. The outputs may be individually switched to a
high impedance state with a HIGH on the respective Output Enable
(E
0
) inputs, allowing the outputs to interface directly with bus oriented
systems. It is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all ON Semiconductor
TTL families.
http://onsemi.com
•
•
•
•
Schottky Process for High Speed
Multifunction Capability
Non-Inverting 3-State Outputs
Input Clamp Diodes Limit High Speed Termination Effects
LOW
POWER
SCHOTTKY
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
– 2.6
24
Unit
V
°C
mA
mA
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
SN74LS253N
SN74LS253D
Package
16 Pin DIP
16 Pin
Shipping
2000 Units/Box
2500/Tape & Reel
©
Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 6
Publication Order Number:
SN74LS253/D
SN74LS253
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
16
E
0b
15
S
0
14
I
3b
13
I
2b
12
I
1b
11
I
0b
10
Z
b
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
E
0a
2
S
1
3
I
3a
4
I
2a
5
I
1a
6
I
0a
7
Z
a
8
GND
LOADING
(Note a)
PIN NAMES
S
0
, S
1
Multiplexer A
E
0a
I
0a
– I
3a
Z
a
Multiplexer B
E
0b
I
0b
– I
3b
Z
b
Common Select Inputs
Output Enable (Active LOW) Input
Multiplexer Inputs
Multiplexer Output
Output Enable (Active LOW) Input
Multiplexer Inputs
Multiplexer Output
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
LOGIC SYMBOL
1
6 5 4
3
10 11 12 13 15
14
2
E I I I I
I I I I E
S
0 0a 0a 1a 2a 3a 0b 1b 2b 3b 0b
S
1
Z
a
Z
b
7
V
CC
= PIN 16
GND = PIN 8
9
http://onsemi.com
2
SN74LS253
LOGIC DIAGRAM
E
0b
15
I
3b
13
I
2b
12
I
1b
11
I
0b
10
S
0
14
S
1
2
I
3a
3
I
2a
4
I
1a
5
I
0a
6
E
0a
1
Z
b
9
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
Z
a
7
FUNCTIONAL DESCRIPTION
The LS253 contains two identical 4-Input Multiplexers
with 3-state outputs. They select two bits from four sources
selected by common select inputs (S
0
, S
1
). The 4-input
multiplexers have individual Output Enable (E
0a
, E
0b
)
inputs which when HIGH, forces the outputs to a high
impedance (high Z) state.
The LS253 is the logic implementation of a 2-pole,
4-position switch, where the position of the switch is
determined by the logic levels supplied to the two select
inputs. The logic equations for the outputs are shown below:
Z
a
= E
0a
⋅(I
0a
⋅S
1
⋅S
0
+ I
1a
⋅S
1
⋅S
0
⋅I
2a
⋅S
1
⋅S
0
+ I
3a
⋅
S
1
⋅S
0
)
Z
b
= E
0b
⋅
(I
0b
S
1
S
0
+ I
1b
⋅
S
1
⋅
S
0
I
2b
⋅
S
1
⋅
S
0
+ I
3b
⋅
S
1
⋅
S
0
)
If the outputs of 3-state devices are tied together, all but
one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.
TRUTH TABLE
SELECT
INPUTS
S
0
X
L
L
H
H
L
L
H
H
S
1
X
L
L
L
L
H
H
H
H
I
0
X
L
H
X
X
X
X
X
X
DATA INPUTS
I
1
X
X
X
L
H
X
X
X
X
I
2
X
X
X
X
X
L
H
X
X
I
3
X
X
X
X
X
X
X
L
H
OUTPUT
ENABLE
E
0
H
L
L
L
L
L
L
L
L
OUTPUT
Z
(Z)
L
H
L
H
L
H
L
H
H = HIGH Level
L = LOW Level
X = Irrelevant
(Z) = High Impedance (off)
Address inputs S
0
and S
1
are common to both sections.
http://onsemi.com
3
SN74LS253
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.4
– 0.65
3.1
0.25
V
O
OL
I
OZH
I
OZL
I
IH
I
IL
I
OS
I
CC
Output LOW Voltage
0.35
Output Off Current HIGH
Output Off Current LOW
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
14
mA
– 30
– 0.4
– 130
12
0.5
20
– 20
20
V
µA
µA
µA
mA
mA
mA
mA
I
OL
= 24 mA
0.4
Min
2.0
0.8
– 1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
= – 18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 12 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
V
CC
= MAX, V
OUT
= 2.7 V
V
CC
= MAX, V
OUT
= 0.4 V
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX, V
E
= 0 V
V
CC
= MAX, V
E
= 4.5 V
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(T
A
= 25°C, V
CC
= 5.0 V) See SN74LS251 for Waveforms
Limits
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay,
Data to Output
Propagation Delay,
Select to Output
Output Enable Time
Output Disable Time
Min
Typ
17
13
30
21
15
15
27
18
Max
25
20
45
32
28
23
41
27
Unit
ns
ns
ns
ns
Figure 1
Figure 1
Figures 4, 5
Figures 3, 5
C
L
= 5.0 pF,
R
L
= 667
Ω
C
L
= 45 pF,
R
L
= 667
Ω
Test Conditions
http://onsemi.com
4
SN74LS253
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
_
10
_
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
_
10
_
0.51
1.01
B
1
8
F
S
C
L
–T–
H
G
D
16 PL
SEATING
PLANE
K
J
T A
M
M
0.25 (0.010)
M
http://onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
