SN54/74LS322A
8-BIT SHIFT REGISTERS
WITH SIGN EXTEND
These 8-bit shift registers have multiplexed input/output data ports to
accomplish full 8-bit data handling in a single 20-pin package. Serial data may
enter the shift-right register through either D0 or D1 inputs as selected by the
data select pin. A serial output is also provided. Synchronous parallel loading
is achieved by taking the register enable and the S / P inputs low. This places
the three-state input / output ports in the data input mode. Data is entered on
the low-to-high clock transition. The data extend function repeats the sign in
the QA flip-flop during shifting. An overriding clear input clears the internal
registers when taken low whether the outputs are enabled or off. The output
enable does not affect synchronous operation of the register.
8-BIT SHIFT REGISTERS
WITH SIGN EXTEND
LOW POWER SCHOTTKY
•
•
•
•
Multiplexed Inputs/ Outputs Provide Improved Bit Density
Sign Extend Function
Direct Overriding Clear
3-State Outputs Drive Bus Lines Directly
(TOP VIEW)
DATA
SIGN
VCC SELECT EXTEND D1
B/QB D/QD
F/QF
H/QH
Q/H
CLOCK
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
19
DS
G
S/P
18
SE
17
D1
16
B/QB
15
D/QD
14
F/QF
13
12
11
20
1
N SUFFIX
PLASTIC
CASE 738-03
H/GH Q/H
CK
D0
A/QA C/QC
E/QE
G/QG
OE
CLR
20
1
DW SUFFIX
SOIC
CASE 751D-03
1
2
3
D0
4
5
6
7
8
9
10
REGISTER S/P
ENABLE
A/QA C/QC
E/QE G/QG OUTPUT CLEAR GND
ENABLE
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Output Current — High
Output Current — Low
Q H
′
Q H
′
Q H
′
QA– QH
QA– QH
QA– QH
QA– QH
Parameter
54
74
54
74
54, 74
54
74
54
74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
– 1.0
– 2.6
12
24
Unit
V
°C
mA
mA
mA
mA
FAST AND LS TTL DATA
5-1
SN54/74LS322A
BLOCK DIAGRAM
REGISTER
ENABLE
G
S/P
SIGN
EXTEND
SE
DATA
SELECT
DS
D1
(1)
(2)
(18)
(17)
(19)
D0
(3)
FOUR
IDENTICAL
CHANNELS
NOT
SHOWN
Q
CK
D Q
CLR
CLOCK
CLEAR
OUTPUT
ENABLE
OE
(11)
(9)
(8)
Q
CK
D Q
CLR
Q
CK
D Q
CLR
Q
CK
D Q
CLR
(12)
QH
(4)
A/QA
(16)
B/QB
(7)
G/QG
(13)
H/QH
FUNCTION TABLE
INPUTS
OPERATION
CLEAR
Clear
Hold
Shift Right
Sign Extend
Load
L
L
H
H
H
H
H
REGISTER
ENABLE
H
X
H
L
L
L
L
S/P
X
H
X
H
H
H
L
SIGN
EXTEND
X
X
X
H
H
L
X
DATA
SELECT
X
X
X
L
H
X
X
OUTPUT
ENABLE
L
L
L
L
L
L
X
CLOCK
X
X
X
↑
↑
↑
↑
INPUTS/OUTPUTS
A/QA
L
L
QA0
D0
D1
QAn
a
B/QB
L
L
QB0
QAn
QAn
QAn
b
C/QC
…
H/QH
L
L
QC0
QBn
QBn
QBn
c
L
L
QH0
QGn
QGn
QGn
h
OUTPUT
Q H
′
L
L
QH0
QGn
QGn
QGn
h
When the output enable is high, the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or
clearing of the register is not affected. If both the register enable input and the S/P input are low while the clear input is low, the register is
cleared while the eight input/output terminals are disabled to the high-impedance state.
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Irrelevant (any input, including transitions)
↑
= Transition from LOW to HIGH level
QA0…QH0 = the level of QA through QH, respectively, before the indicated steady-state conditions were established
QAn…QHn = the level of QA through QH, respectively, before the most recent
↑
transition of the clock
D0, D1 = the level of steady-state inputs at inputs D0 and D1 respectively
a…h = the level of steady-state inputs at inputs A through H respectively
FAST AND LS TTL DATA
5-2
SN54/74LS322A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
Output HIGH Voltage
QA– QH
Output HIGH Voltage
Q H
′
Output LOW Voltage
QA– QH
Output LOW Voltage
Q H
′
Output Off Current HIGH
QA– QH
Output Off Current LOW
QA– QH
Other
A – H,
Data Select
Sign Extend
IIH
Input HIGH Current
Other
Data Select
Sign Extend
A–H
Other
IIL
Input LOW Current
Data Select
Sign Extend
IOS
ICC
Short Circuit Current
(Note 1)
Power Supply Current
Q H
′
QA– QH
– 20
– 30
54
74
54
74
54, 74
74
54, 74
74
2.4
2.4
2.5
2.7
– 0.65
3.2
3.2
3.4
3.4
0.25
0.35
0.4
0.5
0.4
0.5
40
– 400
20
40
60
0.1
0.2
0.3
0.1
– 0.4
– 0.8
– 1.2
–100
–130
60
0.8
– 1.5
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VCC = MAX
VCC = MAX
VCC = MAX
VCC = MAX, VIN = 0.4 V
VCC = MAX, VIN = 5.5 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 2.7 V
VCC = MIN, IOH = MAX
IOL = 12 mA
IOL = 24 mA
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MIN, IOH = MAX
Min
2.0
0.7
V
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VOH
VOL
VOL
IOZH
IOZL
VCC = MAX, VOUT = 2.7 V
VCC = MAX, VOUT = 0.4 V
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-3
SN54/74LS322A
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
fMAX
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Parameter
Maximum Clock Frequency
Propagation Delay, Clock
to QH
′
Propagation Delay, Clear
to QH
′
Propagation Delay, Clock
to QA– QH
Propagation Delay, Clear
to QA– QH
Output Enable Time
Output Disable Time
Min
25
Typ
35
26
22
27
22
16
22
15
15
15
15
35
33
35
33
25
35
35
35
25
25
Max
Unit
MHz
ns
ns
ns
ns
ns
ns
CL = 5.0 pF
CL = 45 pF,
RL = 667
Ω
CL = 15 pF
Test Conditions
AC SETUP REQUIREMENTS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
tW
tW
tW
ts
ts
th
th
trec
Parameter
Clock Pulse Width HIGH
Clock Pulse Width LOW
Clear Pulse Width LOW
Data Setup Time
Select Setup Time
Data Hold Time
Select Hold Time
Recovery Time
Min
25
15
20
20
15
0
10
20
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
VCC = 5.0 V
Test Conditions
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
FAST AND LS TTL DATA
5-4
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