OCTAL D FLIP-FLOP WITH ENABLE;
HEX D FLIP-FLOP WITH ENABLE;
4-BIT D FLIP-FLOP WITH ENABLE
The SN54 / 74LS377 is an 8-bit register built using advanced Low Power
Schottky technology. This register consists of eight D-type flip-flops with a
buffered common clock and a buffered common clock enable.
The SN54 / 74LS378 is a 6-Bit Register with a buffered common enable.
This device is similar to the SN54 / 74LS174, but with common Enable rather
than common Master Reset.
The SN54 / 74LS379 is a 4-Bit Register with buffered common Enable. This
device is similar to the SN54 / 74LS175 but features the common Enable
rather then common Master Reset.
SN54/74LS377
SN54/74LS378
SN54/74LS379
OCTAL D FLIP-FLOP WITH
ENABLE; HEX D FLIP-FLOP
WITH ENABLE; 4-BIT D FLIP-FLOP
WITH ENABLE
LOW POWER SCHOTTKY
•
•
•
•
•
8-Bit High Speed Parallel Registers
Positive Edge-Triggered D-Type Flip Flops
Fully Buffered Common Clock and Enable Inputs
True and Complement Outputs
Input Clamp Diodes Limit High Speed Termination Effects
20
1
J SUFFIX
CERAMIC
CASE 732-03
PIN NAMES
LOADING
(Note a)
HIGH
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
20
1
N SUFFIX
PLASTIC
CASE 738-03
E
D0 – D3
CP
Q0 – Q3
Q0 – Q3
Enable (Active LOW) Input
Data Inputs
Clock (Active HIGH Going Edge) Input
True Outputs (Note b)
Complemented Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
20
1
DW SUFFIX
SOIC
CASE 751D-03
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXDW
SN74LSXXXD
Ceramic
Plastic
SOIC
SOIC
FAST AND LS TTL DATA
5-533
SN54/74LS377
•
SN54/74LS378
•
SN54/74LS379
CONNECTION DIAGRAM DIPS
(TOP VIEW)
SN54 / 74LS377
VCC
20
Q7
19
D7
18
D6
17
Q6
16
Q5
15
D5
14
D4
13
Q4
12
CP
11
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
E
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3
10
GND
SN54 / 74LS378
VCC
16
Q5
15
D5
14
D4
13
Q4
12
D3
11
Q3
10
CP
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
E
2
Q0
3
D0
4
D1
5
Q1
6
D2
7
Q2
8
GND
SN54 / 74LS379
VCC
16
Q3
15
Q3
14
D3
13
D2
12
Q2
11
Q2
10
CP
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
E
2
Q0
3
Q0
4
D0
5
D1
6
Q1
7
Q1
8
GND
FAST AND LS TTL DATA
5-534
SN54/74LS377
•
SN54/74LS378
•
SN54/74LS379
LOGIC DIAGRAMS
SN54 / 74LS377
3
4
7
8
13
14
17
18
E
ENABLE
D0
1
D1
D2
D3
D4
D5
D6
D7
CP
CLOCK
11
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
Q0
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
SN54 / 74LS378
3
4
6
11
13
14
D0
CP
9
D1
D2
D3
D4
D5
CP D
E
Q
1
CP D
E
Q
CP D
E
Q
CP D
E
Q
CP D
E
Q
CP D
E
Q
E
Q0
2
Q1
5
Q2
7
Q3
10
Q4
12
Q5
15
SN54 / 74LS379
4
5
12
13
D0
CP
9
D1
D2
D3
E
1
CP
Q
D
Q
E
CP
Q
D
Q
E
CP
Q
D
Q
E
CP
Q
D
Q
E
Q0
3
Q0
2
Q1
6
Q1
7
Q2
11
Q2
10
Q3
14
Q3
15
FAST AND LS TTL DATA
5-535
SN54/74LS377
•
SN54/74LS378
•
SN54/74LS379
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
54, 74
VOL
Output LOW Voltage
74
Input HIGH Current
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
LS377
LS378
LS379
– 20
0.35
0.5
20
0.1
– 0.4
– 100
28
22
15
V
µA
mA
mA
mA
mA
2.5
2.7
54
74
– 0.65
3.5
3.5
0.25
0.4
Min
2.0
0.7
0.8
– 1.5
Typ
Max
Unit
V
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IIH
IIL
IOS
ICC
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX, NOTE 1
NOTE: With all inputs open and GND applied to all data and enable inputs, ICC is measured after a momentary GND, then 4.5 V is applied to clock.
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
fMAX
tPLH
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay,
Clock to Output
Min
30
Typ
40
17
18
27
27
Max
Unit
MHz
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
tW
ts
ts
th
Parameter
Any Pulse Width
Data Setup Time
Enable Setup
Time
Any Hold Time
Inactive — State
Active — State
Min
20
20
10
25
5.0
Typ
Max
Unit
ns
ns
ns
ns
ns
VCC = 5.0 V
Test Conditions
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
FAST AND LS TTL DATA
5-536
SN54/74LS377
•
SN54/74LS378
•
SN54/74LS379
TRUTH TABLE
E
H
L
L
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
CP
Dn
X
H
L
Qn
No
Change
H
L
Qn
No
Change
L
H
AC WAVEFORMS
SN54 / 74LS377
1/fmax
tW
CP
1.3 V
ts(H)
ts(L)
th(H)
1.3 V
tPLH
Q
1.3 V
1.3 V
CP
1.3 V
ts(H)
SN54 / 74LS378
1/fmax
tW
1.3 V
ts(L)
th(H)
E, D
th(L)
th(L)
1.3 V
tPHL
1.3 V
Q
D OR E
*
*
1.3 V
tPHL
1.3 V
1.3 V
tPLH
1.3 V
Figure 1. Clock to Output Delays Clock Pulse
Width, Frequency, Setup and Hold Times Data
or Enable to Clock
Figure 2. Clock to Output Delays Clock Pulse
Width, Frequency, Setup and Hold Times Data
or Enable to Clock
SN54 / 74LS379
1/fmax
tW
CP
1.3 V
ts(H)
ts(L)
1.3 V
th(H)
th(L)
E, D
*
1.3 V
tPLH
1.3 V
1.3 V
tPHL
1.3 V
Q
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 3. Clock to Output Delays Clock Pulse
Width, Frequency, Setup and Hold Times Data,
Enable to Clock
FAST AND LS TTL DATA
5-537
stm32/stm8
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