RNA51xx Series
CMOS system–RESET IC
REJ03D0505-0300
Rev.3.00
Oct 10, 2008
General Description
The RNA51xx series provide system reset signal for microprocessor and electrical systems.
Threshold voltage is 1.4 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.4 V, 4.5 V, 4.6 V, 5.0 V and accuracy is
±1.0%.
The reset output delay time can be set by external capacitor connected to CD pin.
Manual reset input is available and input resistance is 2 MΩ typ.
This series have two output types (active-low CMOS output and active-low open-drain output).
Features
•
•
•
•
•
•
•
•
•
•
Threshold voltage: 1.4 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.4 V, 4.5 V, 4.6 V, 5.0 V
Threshold voltage accuracy:
±1.0%
Threshold voltage hysteresis: 5% typ.
Low supply current: 0.7
µA
typ.
Capacitor-adjustable output delay time
Manual reset
VOUT
CMOS output, or open-drain output
5-pin SOT-23 package
Temperature range: –40°C to 85°C
Ordering Information
Part Name
RNA51A26FLPEL
RNA51A27FLPEL
RNA51A28FLPEL
RNA51A29FLPEL
RNA51A30FLPEL
RNA51A31FLPEL
RNA51A44FLPEL
RNA51A45FLPEL
RNA51A46FLPEL
RNA51B14FLPEL
RNA51B27FLPEL
RNA51B50FLPEL
Package Type
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
MPAK-5pin
Package Code
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
PLSP0005ZB-A
Package
Abbreviation
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
LP
Taping Abbreviation
(Quantity)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
EL (3,000pcs/Reel)
Applications
•
•
•
•
•
Power supply voltage monitoring for microprocessors
Battery-powered portable equipment
Computers and notebook computers
Wireless Communication Systems
Digital still camera, digital video camera, PDA
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 1 of 11
RNA51xx Series
Pin Arrangement
VOUT
1
VDD 2
GND 3
5 CD
4 MR
(Top view)
Product list
Threshold Voltage –V
TH
[V]
1.4
2.6
2.7
2.8
2.9
3.0
3.1
4.4
4.5
4.6
5.0
Open-Drain output
Type No.
—
RNA51A26FLP
RNA51A27FLP
RNA51A28FLP
RNA51A29FLP
RNA51A30FLP
RNA51A31FLP
RNA51A44FLP
RNA51A45FLP
RNA51A46FLP
—
Marking
—
5N
5P
5Q
5R
5S
5T
6G
6H
6J
—
CMOS output
Type No.
RNA51B14FLP
—
RNA51B27FLP
—
—
—
—
—
—
—
RNA51B50FLP
Marking
6P
—
7C
—
—
—
—
—
—
—
3R
Outline and Article Indication
• RNA51A26FLP (Example)
Marking
Control Code
5
MPAK-5
N
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 2 of 11
RNA51xx Series
Functional block diagram & typical application circuit
(1) RNA51Axx Products
Power
supply
MR
VDD
2
4
Power
supply
delay
1
VOUT
RESET
Microprocessor
Vref
GND
3
5
CD
(2) RNA51Bxx Products
Power
supply
MR
VDD
2
4
delay
1
VOUT
RESET
Microprocessor
Vref
GND
3
5
CD
Notes: 1. It is good for stable operation to use a decoupling capacitor with excellent high frequency characteristics
between VDD and GND pin.
2. Capacitor value is determined by system conditions.
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 3 of 11
RNA51xx Series
Timing Diagram
V
HYS
V
TH
VDD
MR
t
DLY
t
DLY
t
DLY
VOUT
Absolute Maximum Ratings
(1) RNA51Axx Products
Temperature condition Ta = 25°C
Item
Supply voltage
Output voltage
Input voltage
Output current
Continuous power dissipation
Operating temperature range
Storage temperature range
Symbol
V
DD
V
OUT
V
IN
I
OUT
P
D
T
OPR
T
STG
Pin
V
DD
V
OUT
MR, MD
V
OUT
—
—
—
Ratings
6.0
–0.3 to 6.0
–0.3 to V
DD
+0.3
±50
120
–40 to +85
–55 to +125
Unit
V
V
V
mA
mW
°C
°C
(2) RNA51Bxx Products
Temperature condition Ta = 25°C
Item
Supply voltage
Output voltage
Input voltage
Output current
Continuous power dissipation
Operating temperature range
Storage temperature range
Symbol
V
DD
V
OUT
V
IN
I
OUT
P
D
T
OPR
T
STG
Pin
V
DD
V
OUT
MR, MD
V
OUT
—
—
—
Ratings
6.0
–0.3 to V
DD
+0.3
–0.3 to V
DD
+0.3
±50
120
–40 to +85
–55 to +125
Unit
V
V
V
mA
mW
°C
°C
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 4 of 11
RNA51xx Series
Electrical characteristics
(1) RNA51Axx Products
Temperature condition Ta = 25°C
Item
Supply voltage
Supply current
Threshold voltage
Temperature coefficiency of the
thereshold voltage
(Reference value)
Threshold voltage hysteresis
VOUT
low-level output current
Symbol
V
DD
I
DD
–V
TH
∆(–V
TH
)
–V
TH
⋅∆Ta
V
HYS
I
OL
Min
1.1
–V
TH
×0.99
Typ
0.7
±100
Max
5.5
4.2
–V
TH
×1.01
Unit
V
µA
V
ppm/
°C
V
mA
Ta = –40 to 85°C
Conditions
pull-up resistor = 470 kΩ
V
OUT
≤
0.1×VDD
V
DD
= 5.5 V
–V
TH
×3%
0.2
3.4
10
V
DD
×0.75
1
–V
TH
×5%
1.2
7.0
20
2
–V
TH
×8%
0.1
35
V
DD
×0.25
7
VOUT
Output leakage current
(open drain output)
Note1
Delay time
MR Low-level input voltage
MR High-level input voltage
MR internal pull-up resistance
Note2
I
LEAK
t
DLY
V
IL
V
IH
R
MR
µA
ms
V
V
MΩ
V
DD
= 1.3 V
V
DD
= 2.4 V
(–V
TH
≥
2.7 V)
V
DD
= V
OUT
= 5.5 V
V
DD
= 1.1 to 5.5V, t
TLH
= 1
µs
C
D
= 4.7 nF
V
OUT
= 0.5 V
(2) RNA51Bxx Products
Temperature condition Ta = 25°C
Item
Supply voltage
Supply current
Threshold voltage
Threshold voltage
temperature dependency
(Reference value for design)
Threshold voltage hysteresis
VOUT
low-level output current
Symbol
V
DD
I
DD
–V
TH
∆(–V
TH
)
–V
TH
⋅∆Ta
V
HYS
I
OL
Min
1.1
–V
TH
×0.99
Typ
0.7
±100
Max
5.5
4.2
–V
TH
×1.01
Unit
V
µA
V
ppm/
°C
V
mA
Ta = –40 to 85°C
Conditions
pull-up resistor = 470 kΩ
V
OUT
≤
0.1×VDD
V
DD
= 5.5 V
–V
TH
×3%
0.2
3.4
–1.4
–1.5
10
V
DD
×0.75
1
–V
TH
×5%
1.2
7.0
–2.7
–3.0
20
2
–V
TH
×8%
35
V
DD
×0.25
7
VOUT
High-level output current
(CMOS output)
Delay time
Note1
I
OH
mA
t
DLY
Note2
ms
V
V
MΩ
V
DD
= 1.3 V
V
DD
= 2.4 V
(–V
TH
≥
2.7 V)
V
OUT
=
V
DD
= 4.5 V
V
DD
–0.5 V
(–V
TH
≤
4.0 V)
V
DD
= 5.5 V
V
DD
= 1.1 to 5.5 V, t
TLH
= 1
µs
C
D
= 4.7 nF
V
OUT
= 0.5 V
MR Low-level input voltage
MR High-level input voltage
MR internal pull-up resistance
Note:
V
IL
V
IH
R
MR
1. Delay time is specified when charging starts in the condition that CD pin is completely discharged. When discharging of CD
pin is not complete because of immediate stop and other reasons, the delay time is not guaranteed. Therefore, when
passing of VDD pin input voltage immediately stops (the period of condition that VDD pin input voltage is lower than the
detected voltage is short), discharging of external capacitor CD is inadequate, and the delay time becomes much shorter
than the minimum guaranteed value. Be sure to fully check that there are no problems as the system.
2. Minimum value of low-pulse width to be input to MR pin depends on the value of external capacitor CD. Therefore, set the
low-pulse width to be input to MR pin to the minimum input low-pulse width shown in figure 1 or more.
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
Page 5 of 11
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