Radial Leaded,
Epoxy Dipped,
Multilayer Ceramic Capacitors
RD
Series
MERITEK
MERITEK
Radial Leaded, Epoxy Dipped Multilayer Ceramic
Capacitors are constructed with a moisture and shock resistant
epoxy coating, and can be supplied in bulk or tape and reel
packaging for automatic insertion in printed circuit boards. They
have a wide range of applications in computers, data processors,
telecommunication, industrial controls and instrumentation
equipment, etc.
P
ART
N
UMBERING
S
YSTEM
RD
Meritek Series
Size
Dielectric
CODE
CG
NPO
101
100
-
--
-
J
± 5%
500
50V
K
±10%
101
100V
Blank
Bulk
XR
X7R
223
22000
0.022
M
±20%
201
200V
RR
Radial Leaded, Reel
Package
YV
Y5V
104
100000
0.1
Z
+80% to –20%
15
YV
104
Z
500
RR
Capacitance Code
CODE
(pF)
(μF)
Tolerance
CODE
Rated Voltage
CODE
Packaging
CODE
Lead Spacing
RD15
2.5 + 0.8
(.10 + 0.032)
1.50(.060)
max.
Size Code and Dimensions in mm (inches)
RD20
5.08
(.200)
max.
3.81(.150)
max
4.06
(.160)
max.
5.08(.200)
max
1.50(.060)
25.4(1.00)
max
max.
25.4(1.00)
max
RD16
4.06
(.160)
max.
RD21
5.08
(.200)
max.
7.60(.300)
max.
5.0 + 0.8
(.20 + 0.032)
3.81
max.
(.150)
5.08
max.
(.200)
7.60(.300)
max.
25.4(1.00)
max
25.4(1.00)
max
RD30
7.60
(.300)
max.
Lead length can be cut upon customer's request.
7.60(.300)
max.
5.0 + 0.8
(.20 + 0.032)
1.50(.060)
max.
25.4(1.00)
max
Standard cut lead lengths are: 3.3 + 0.8(.13 + .03)
6.0 + 1.0(.24 + .04)
10.0 + 2.0(.39 + .08)
Specifications are
subject to change without notice.
Special lead styles available upon request.
rev.6a
Radial Leaded,
Epoxy Dipped
Multilayer Ceramic Capacitors
RD
Series
MERITEK
P
ERFORMANCE
S
PECIFICATIONS
1.E
LECTRICAL
DIELECTRIC
CODE
EIA
NPO
0 ± 3 0 p p m /
o
C , C > 20pF
0 +120 /- 4 0 ppm / C , C < 2 0 p F
o
X7R
C ±15% maximum
Over - 5 5
o
C to +125
o
C
Y5V
C ± 2 2 % / 82% maximum
-
Over -30
o
C to +85
o
C
Temperature Characteristic
EIA
Operating Temperature Range
Measuring Conditions for
Capacitance and D.F.
Dissipation Factor (D.F.)
and Tangent of Loss
Angle (tan )
Insulation Resistance (I.R.)
after 60 secs, charging at
rated
voltage, 25
o
C , 5 5% RH max .
Voltage Proof 25
o
C , 1 - 5 s e c s
Capacitance Aging
- 5 5
o
C to + 125
o
C
1 MHz, 1 Vrms, C < 1000pF
- 5 5
o
C to +125
o
C
1 KHz, 1 Vrms
- 3 0
o
C to +85
o
C
1 KHz, 0.5 Vrms
< 0.1%
< 2 .5 %
< 5 .0 %
> 100G ohms or > 1 0 0 0 M
μ
F
Whichever is less
> 1 0 0G ohms or > 1 0 0 0 M
μ
F
Whichever is less
> 10G ohms or > 1 0 0 0 M
μ
F
Whichever is less
2.5 x Rated Voltage
0
2.5 x Rated Voltage
2.5% per decade hour
2.5 x Rated Voltage
7% per decade hour
2.E
NVIROMENTAL
Test
Solderability
Test Condition
Solder 60Sn/40Pb, 235 ±5
o
C
Immers ion 2 ±0 .5 s ec .
Depth of Immersion: 1.5 – 2.0mm
Immersion in solder bath at 260 ±5
o
C f o r 1 0 ± 1 s e c .
Recovery: 24 ±2 hrs. (NPO)
48 ±4 hrs. (X7R, Y5V)
Post-Test Inspection Requirements
At least 95% of leads should be well tinned
No visible damage.
Resistance to
Soldering Heat
NPO
C /
o
C
< ±5%
X7R
±10%
Y5V
± 20%
Rapid Change
Of Temperature
-55 to +125
o
C ( N P O . X 7 R )
- 2 5 T O + 8 5
o
C (Y5V)
5 cycles, duration : 30 mins.
Recovery: 24 ±2 hrs. (NPO)
48 ±4 hrs. (X7R, Y5V)
No visible damage
No visible damage
Endurance
1000 hrs. at maximum temperature with 1.5 x rated
voltage applied
Recovery: 24 ±2 hrs. (NPO)
48 ±4 hrs. (X7R, Y5V)
C /
o
C
DF
IR
NPO
< ±2%
< 0.3%
X7R
< ±2 0 %
< 5%
R.C>25S
Y5V
< ±3 0 %
< 10%
3.Capacitance Range
SIZE
RD15, RD16
RD20, RD21
NPO
10pF
to
1000pF
X7R
1000pF
to
0.1μF
0.1μF
to 1.0μF
Y5V
8200pF
to
0.1μF
0.15μF
to
1μF
FPGA/CPLD
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