PTN3360B
Enhanced performance HDMI/DVI level shifter
Rev. 02 — 8 October 2009
Product data sheet
1. General description
The PTN3360B is a high-speed level shifter device which converts four lanes of low-swing
AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain
current-steering differential output signals, up to 2.5 Gbit/s per lane. Each of these lanes
provides a level-shifting differential buffer to translate from low-swing AC-coupled
differential signaling on the source side, to TMDS-type DC-coupled differential
current-mode signaling terminated into 50
Ω
to 3.3 V on the sink side. Additionally, the
PTN3360B provides a single-ended active buffer for voltage translation of the HPD signal
from 5 V on the sink side to 3.3 V on the source side and provides a channel for level
shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V
source-side and 5 V sink-side. The DDC channel is implemented using pass-gate
technology providing level shifting as well as disablement (isolation between source and
sink) of the clock and data lines.
The low-swing AC-coupled differential input signals to the PTN3360B typically come from
a display source with multi-mode I/O, which supports multiple display standards, e.g.,
DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI
or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or
HDMI v1.3a specification. By using PTN3360B, chip set vendors are able to implement
such reconfigurable I/Os on multi-mode display source devices, allowing the support of
multiple display standards while keeping the number of chip set I/O pins low. See
Figure 1.
The PTN3360B main high-speed differential lanes feature low-swing self-biasing
differential inputs which are compliant to the electrical specifications of
DisplayPort
Standard v1.1
and/or
PCI Express Standard v1.1,
and open-drain current-steering
differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical specifications. The
I
2
C-bus channel level-translates the DDC signals between 3.3 V (source) and 5.0 V (sink).
The PTN3360B is a fully featured HDMI as well as DVI level shifter. It is functionally
equivalent to PTN3300A but provides higher speed performance and higher ESD
robustness. The PTN3360B is also equivalent to PTN3360A with the exception that
PTN3360B provides non-inverting level shifting on the HPD channel.
PTN3360B is powered from a single 3.3 V power supply consuming a small amount of
power (120 mW typ.) and is offered in a 48-terminal HVQFN48 package.
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
2. Features
2.1 High-speed TMDS level shifting
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Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and
HDMI v1.3a compliant open-drain current-steering differential output signals
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TMDS level shifting operation up to 2.5 Gbit/s per lane (250 MHz character clock)
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Integrated 50
Ω
termination resistors for self-biasing differential inputs
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Back-current safe outputs to disallow current when device power is off and monitor is
on
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Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting
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Integrated DDC level shifting (3.3 V source to 5 V sink side)
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0 Hz to 400 kHz I
2
C-bus clock frequency
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Back-power safe sink-side terminals to disallow backdrive current when power is off or
when DDC is not enabled
2.3 HPD level shifting
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HPD non-inverting level shift from 5 V on the sink side to 3.3 V on the source side, or
from 0 V on the sink side to 0 V on the source side
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Integrated 200 kΩ pull-down resistor on HPD sink input guarantees ‘input LOW’ when
no display is plugged in
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Back-power safe design on HPD_SINK to disallow backdrive current when power is off
2.4 General
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I
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Power supply 3.3 V
±
10 %
ESD resilience to 8 kV HBM, 500 V CDM
Power-saving modes (using output enable)
Back-current-safe design on all sink-side main link, DDC and HPD terminals
Transparent operation: no re-timing or software configuration required
3. Ordering information
Table 1.
Ordering information
Package
Name
PTN3360BBS
HVQFN48
Description
Version
plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; SOT619-1
body 7
×
7
×
0.85 mm
Type number
PTN3360B_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 8 October 2009
3 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
5. Pinning information
5.1 Pinning
48 IN_D4+
46 V
DD
45 IN_D3+
42 IN_D2+
40 V
DD
39 IN_D1+
47 IN_D4−
44 IN_D3−
41 IN_D2−
38 IN_D1−
43 GND
terminal 1
index area
GND
V
DD
n.c.
n.c.
GND
REXT
HPD_SOURCE
SDA_SOURCE
SCL_SOURCE
1
2
3
4
5
6
7
8
9
37 GND
36 GND
35 n.c.
34 n.c.
33 V
DD
32 DDC_EN
31 GND
30 HPD_SINK
29 SDA_SINK
28 SCL_SINK
27 GND
26 V
DD
25 OE_N
GND 24
002aae269
PTN3360BBS
n.c. 10
V
DD
11
GND 12
OUT_D4+ 13
OUT_D4− 14
V
DD
15
OUT_D3+ 16
OUT_D3− 17
GND 18
OUT_D2+ 19
OUT_D2− 20
V
DD
21
OUT_D1+ 22
OUT_D1− 23
Transparent top view
HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND
pins must be connected to supply ground for proper device operation. For enhanced thermal,
electrical, and board level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board and for proper heat conduction through the board,
thermal vias need to be incorporated in the PCB in the thermal pad region.
Fig 3.
Pin configuration for HVQFN48
PTN3360B_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 8 October 2009
5 of 22
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