Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
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Features
• Supports AT&T TR62411 Stratum 3, 4 and
Stratum 4 Enhanced for DS1 interfaces and for
ETSI ETS 300 011, TBR 4, TBR 12, and TBR
13 for E1 interfaces
• Supports ITU-T G.812 Type IV clocks for
1.544kbit/s interfaces and 2.048kbit/s interface
•
Introduction
PT7A4410/4410L employs a digital phase-locked
loop (DPLL) to provide timing and synchronizing
signals for multitrunk T1 and E1 primary rate
transmission links, and for STS-3/OC3 links. The ST-
BUS clock and framing signals are phase-locked to
input reference signals of either 2.048 MHz,
1.544MHz or 8 kHz.
The PT7A4410/4410L meets the requirements for
AT&T TR62411 Stratum 3, 4 and Stratum 4 En-
hanced, and ETSI ETS 300 011 in jitter tolerance,
jitter transfer, intrinsic jitter, frequency accuracy, hold-
over accuracy, capture range, phase slope and MTIE,
etc.
The PT7A4410/4410L operates in Manual or Auto-
matic Mode, and in each of the modes, three operat-
ing states are available: Normal, Holdover and Free-
Run.
Provides C1.5, C3, C2, C4, C8, C6, C16 and C19
output clock signals
Provides five kinds of 8kHz ST-BUS framing
signals
Two independent reference inputs
Input reference frequency 1.544MHz, 2.048MHz
or 8kHz selectable
Provides bit error free reference switching and
meets phase slope and MTIE requirements
Normal, Holdover or Free-Run operating modes
available
Holdover accuracy: ±0.2ppm
Automatic reference input impairment monitor
Power supply: 5V (4410) and 3.3V(4410L)
•
•
•
•
•
•
•
•
Applications
• Synchronization and timing control for multitrunk
T1 and E1 systems, STS-3/OC3 systems
•
•
Ordering Information
Pa r t Nu m b er
PT7A4410J
PT7A4410LJ
Pa ck a ge
44-Pin PLCC
44-Pin PLCC
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
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Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
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Contents
Features ....................................................................................................................................................... 1
Applications ................................................................................................................................................ 1
Introduction ................................................................................................................................................. 1
Ordering Information .................................................................................................................................. 1
Block Diagram ............................................................................................................................................ 3
Pin Information ........................................................................................................................................... 4
Pin Assignment ..................................................................................................................................... 4
Pin Configuration ................................................................................................................................. 4
Pin Description ..................................................................................................................................... 5
Functional Description ................................................................................................................................ 7
Overall Operation ................................................................................................................................. 7
Modes and States of Operation ........................................................................................................... 10
Applications Information .................................................................................................................... 14
Detailed Specifications .............................................................................................................................. 16
Definitions of Critical Performance Specifictions ............................................................................... 16
Absolute Maximum Ratings ............................................................................................................... 18
Recommended Operating Conditions ................................................................................................. 18
DC Electrical and Power Supply Characteristics ................................................................................ 19
AC Electrical Characteristics .............................................................................................................. 20
Mechanical Specifications ......................................................................................................................... 33
Note .......................................................................................................................................................... 34
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Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
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Block Diagram
Figure 1. Block Diagram
RST
TCLR
V
CC
GND
OSCi
OSCo
TCK
TDI
TMS
TRST
TDO
PRI
SEC
Master
Clock
TIE
Corrector
Virtual
Reference
DPLL
APLL
IEEE 1149.1a
State
Select
Reference
Select MUX
State
Select
Input
Impairment
Monitor
Output
Interface
Circuit
TIE
Correct
Enable
ACKi
ACKo
C1.5
C2
C3
C4
C6
C8
C16
C19
F0
F8
F16
RSP
TSP
RSEL
LOS1
LOS2
Mode/State
Control Machine
Guard
Time
Circuit
Feedback
Frequency
Select MUX
HOLDOVER
MS1
MS2
GTo
GTi
FS1
FS2
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Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
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Pin Information
Pin Assignment
Table 1. Pin Assignment
G r ou p
Chip Clock
Power & Ground
Clock and Framing Outputs
Control Signals
Reference Inputs
IEEE 1149.1a
Symb ol
OSCi, OSCo, ACKi, ACKo
V
CC
, AVDD, GND, AGND
C1.5, C3, C2, C4, C6, C8, C16, C19,
F0, F8, F16, RSP, TSP
RSEL, LOS1, LOS2, MS1, MS2, GTi,
GTo, FS1, FS2, RST, TCLR
PRI, SEC
TCK, TDI, TMS, TRST, TDO
F u n ct ion
Clock
Power
Clock and Framing Signals
Control
Reference Clock
IEEE 1149.1a Interface
Pin Configuration
Figure 2. Pin Configuration
6
4
3
2
1
44
43
42
41
V
CC
OSCo
OSCi
AGND
F16
RSP
F0
TSP
F8
C1.5
AVDD
40
5
PRI
SEC
TRST
TCLR
TCK
GND
TMS
RST
TDI
FS1
FS2
7
8
9
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
18
19
28
39
38
37
36
44-Pin PLCC
35
34
33
32
31
30
29
TEST
RSEL
MS1
MS2
TDO
LOS1
LOS2
GTo
GND
GTi
HOLDOVER
PT0106(09/02)
C3
C2
C4
C19
ACKi
GND
ACKo
C8
C16
C6
V
CC
Top View
4
Ver:0
Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
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Pin Description
Table 2. Pin Description
P in
1, 23, 31
10
2
Na m e
GND
AGND
TCK
Typ e
Ground Digit a l G r ou n d (0V)
Ground An a log G r ou n d
I
Test C lock (T T L I n p u t ): Provides the clock to the JTAG test logic. This pin is internally
pulled up to V
CC
.
T I E cir cu it r eset (T T L ): A low level on this pin will reset the TIE circuit, re-aligning
the output signals with the input signal. TCLR must be active (low) for at least 300ns.
This pin is internally pulled down to GND.
Test R eset (T T L I n p u t ): Asynchronously initializes the JTAG TAP controller by putting
it in the Test-Logic-Reset state. This pin is internally pulled down to GND.
Secon d a r y r efer en ce (T T L ): One of two independent input reference signals, internally
pulled down to GND.
P r im a r y r efer en ce (T T L ): The other independent reference signal, internally pulled
down to GND.
Power su p p ly +5V DC for PT7A4410J. +3.3V DC for PT7A4410LJ
O scilla t or m a st er clock ou t p u t (C MO S): Output of 20MHz master clock
O scilla t or m a st er clock in p u t (C MO S): Input of 20MHz master clock (can be connected
directly to a clock source)
F r a m e p u lse ST-BUS 16.384Mb /s (C MO S): 8kHz frame signal with 61ns low level pulse
that marks the beginning of a ST-BUS frame, typically used for ST-BUS opetation at
8.192Mb/s. See figure 18.
R eceive Syn c P u lse (C MO S O u t p u t ). This is an 8kHz 488ns active high framing pulse,
which marks the end of an ST-BUS frame. See Figure 19.
F r a m e p u lse ST-BUS 2.048 Mb /s (C MO S): 8kHz frame signal with 244ns low level
pulse that marks the beginning of a ST-BUS frame e, typically used for ST-BUS opetation
at 2.048Mb/s. See figure 18.
Tr a n sm it Syn c P u lse (C MO S O u t p u t ). This is an 8kHz 488ns active high framing pulse,
which marks the beginning of an ST-BUS frame. See Figure 19.
F r a m e p u lse ST-BUS 8.192 Mb /s (C MO S): 8kHz frame signal with 122ns high level
pulse that marks the beginning of a ST-BUS frame
1.544 MH z clock (C MO S): This output is used in T1 applications.
An a log Power Su p p ly: +5V DC for PT7A4410J. +3.3V DC for PT7A4410LJ
3.088 MH z clock (C MO S): This output is used in T1 applications.
2.048 MH z clock (C MO S): This output is used for ST-BUS operation at 2.048Mb/s.
4.096 MH z clock (C MO S): This output is used for ST-BUS operation at 2.048Mb/s and
4.096Mb/s.
C lock 19.44MH z (C MO S O u t p u t ). This output is used in OC3/STS-3 applications.
An a log P L L C lock I n p u t (C MO S I n p u t ). This input clock is a reference for an internal
analog PLL. This pin is internally pulled down to GND.
An a log P L L C lock O u t p u t (C MO S O u t p u t ). This output clock is generated by the
internal analog PLL.
Descr ip t ion
3
TCLR
I
4
5
6
7, 28
8
9
TRST
SEC
PRI
V
CC
OSCo
OSCi
I
I
I
Power
O
I
11
F16
O
12
RSP
O
13
F0
O
14
15
16
17
18
19
20
21
22
24
TSP
F8
C1.5
AVDD
C3
C2
C4
C19
ACKi
ACKo
O
O
O
Power
O
O
O
O
I
O
PT0106(09/02)
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