TAS2521
www.ti.com
SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
Digital Input Class-D Speaker Amplifier with Embedded miniDSP and mono headphone
amplifier
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TAS2521
1 INTRODUCTION
1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
1
•
Digital Input Mono Speaker Amp
Instruction-Programmable Embedded miniDSP
Supports 8-kHz to 192-kHz Sample Rates
Mono Class-D BTL Speaker Driver (2 W Into
4
Ω
or 1.7 W Into 8
Ω)
Mono Headphone Driver
Two Single-Ended Inputs With Output Mixing
and Level Control
Embedded Power-on-Reset
Integrated LDO
Built-in Digital Audio Processing Blocks With
User-Programmable Biquad Filters
Integrated PLL Used for Programmable Digital
Audio Processor
I
2
S, Left-Justified, Right-Justified, DSP, and
TDM Audio Interfaces
I
2
C and SPI control with auto-increment
Full Power-Down Control
Power Supplies:
– Analog: 1.5 V–1.95 V
– Digital Core: 1.65 V–1.95 V
– Digital I/O: 1.1 V–3.6 V
– Class-D: 2.7 V–5.5 V (SPKVDD
≥
AVDD)
24-Pin QFN Package (4mm × 4mm)
1.2
•
•
•
Applications
Portable Audio Devices
White goods
Portable Navigation Devices
1.3
Description
The TAS2521 is a low power digital input speaker
amp with support for 24-bit digital I2S data mono
playback.
In addition to driving a speaker amp upto 4-Ω, the
device also features a mono headphone driver and a
fully programmable miniDSP for signal processing.
The digital audio data format is programmable to
work with popular audio standard protocols (I
2
S,
left/right-justified) in master, slave, DSP and TDM
modes. The fully programmable miniDSP can support
several functions such equalization for audio, multi-
band DRC, tone generation and several other user
defined functions. An on-chip PLL provides the high-
speed clock needed by the digital signal-processing
block. The volume level can be controlled by register
control. The audio functions are controlled using the
I
2
C™ serial bus or SPI bus. The device includes an
on-board LDO that runs off the speaker power supply
to handle all internal device analog and digital power
needs. The included POR as power-on-resetcircuit
reliably resets the device into its default state so no
external reset is required at normal usage; however,
the device does have a reset pin for more complex
system initialization needs. The device also includes
two analog inputs for mixing and muxing in both
speaker and headphone analog paths.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TAS2521
SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AINR
AINL
0 dB to -78 dB and Mute
(Min 0.5 dB steps)
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
6 dB to +24 dB
(6 dB steps)
DAC Signal
Proc.
Dig
Vol
Mono
6
'
DAC
6
-6 dB to +29 dB
and Mute
(1 dB steps)
SPKP
SPKM
miniDSP
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
6
POR
HPOUT
Data
Interface
LDO
LDO_SEL
SPKVDD
SPI_SEL
RST
SPI/I
2
C
Control Block
Secondary I
2
S
Interface
Primary I
2
S
Interface
AVDD
Supplies
PLL
Interrupt
Control
DVDD
IOVDD
SPKVSS
AVSS
DVSS
Pin Muxing / Clock Routing
SDA/MOSI
GPIO/DOUT
SCL/SSZ
SCLK
MISO
WCLK
Figure 1-1. Simplified Block Diagram
NOTE
This data manual is designed using PDF document-viewing features that allow quick access
to information. For example, performing a global search on "page 0 / register 27" produces
all references to this page and register in a list. This makes is easy to traverse the list and
find all information related to a page and register. Note that the search string must be of the
indicated format. Also, this document includes document hyperlinks to allow the user to
quickly find a document reference. To come back to the original page, click the green left
arrow near the PDF page number at the bottom of the file. The hot-key for this function is alt-
left arrow on the keyboard. Another way to find information quickly is to use the PDF
bookmarks.
2
INTRODUCTION
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TAS2521
MCLK
BCLK
DIN
Copyright © 2013, Texas Instruments Incorporated
TAS2521
www.ti.com
SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
2 PACKAGE AND SIGNAL DESCRIPTIONS
2.1
Package/Ordering Information
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
RGE
OPERATING
TEMPERATURE
RANGE
–40°C to 85°C
ORDERING NUMBER
TAS2521IRGET
TAS2521IRGER
TRANSPORT MEDIA,
QUANTITY
Tape and reel, 250
Tape and reel, 3000
TAS2521
QFN-24
2.2
Device Information
RGE PACKAGE
(TOP VIEW)
SDA/MOSI
20
SCL/SSZ
19
18
17
16
15
14
7
AVDD
8
LDO_SEL
9
SPKM
10
SPKVDD
11
SPKVSS
13
12
SPKP
IOVDD
DVDD
DVSS
24
SPI_SEL
RST
AINL
AINR
HPOUT
AVSS
1
2
3
4
5
6
23 22
21
SCLK
GPIO/DOUT
MISO
MCLK
BCLK
WCLK
DIN
Table 2-1. RGE PIN FUNCTIONS
PIN
NAME
SPI_SEL
RST
AINL
AINR
HPOUT
AVSS
AVDD
LDO_SEL
SPKM
SPKVDD
SPKVSS
SPKP
DIN
WCLK
BCLK
MCLK
(1)
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
(1)
I
I
I
I
O
GND
PWR
I
O
PWR
PWR
O
I
I/O
I/O
I
DESCRIPTION
Selects between SPI and I2C digital interface modes; (1 = SPI mode) (0 = I2C mode)
Reset for logic, state machines, and digital filters; asserted LOW.
Analog single-ended line left input
Analog single-ended line right input
Headphone and Lineout Driver Output
Analog Ground, 0V
Analog Core Supply Voltage, 1.5V - 1.95V, tied internally to the LDO output
Select Pin for LDO; ties to either SPKVDD or SPKVSS
Class-D speaker driver inverting output
Class-D speaker driver power supply
Class-D speaker driver power supply ground supply
Class-D speaker driver non-inverting output
Audio Serial Data Bus Input Data
Audio Serial Data Bus Word Clock
Audio Serial Data Bus Bit Clock
Master CLK Input / Reference CLK for CLK Multiplier - PLL (On startup PLLCLK = CLKIN)
I = Input, O = Output, GND = Ground, PWR = Power, Z = High Impedance
PACKAGE AND SIGNAL DESCRIPTIONS
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3
Copyright © 2013, Texas Instruments Incorporated
TAS2521
SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
www.ti.com
Table 2-1. RGE PIN FUNCTIONS (continued)
PIN
NAME
MISO
GPIO/DOUT
SCL/SSZ
SDA/MOSI
SCLK
IOVDD
DVDD
DVSS
NO.
17
18
19
20
21
22
23
24
I/O
(1)
O
I/O/Z
I
I
I
PWR
PWR
GND
SPI Serial Data Output
GPIO / Audio Serial Bus Output
Either I2C Input Serial Clock or SPI Chip Select Signal depending on SPI_SEL state
Either I2C Serial Data Input or SPI Serial Data Input depending on SPI_SEL state.
Serial clock for SPI interface
I/O Power Supply, 1.1V - 3.6V
Digital Power Supply, 1.65V - 1.95V
Digital Ground, 0V
DESCRIPTION
3 ELECTRICAL SPECIFICATIONS
3.1
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
AVDD to AVSS
DVDD to DVSS
SPKVDD to SPKVSS
IOVDD to IOVSS
Digital input voltage
Analog input voltage
Operating temperature range
Storage temperature range
Junction temperature (T
J
Max)
QFN
(1)
Power dissipation(with thermal pad soldered to board)
–0.3
–0.3
–0.3
–0.3
IOVSS – 0.3
AVSS – 0.3
–40
–55
MAX
2.2
2.2
6
3.9
IOVDD + 0.3
AVDD + 0.3
85
150
105
(T
J
Max – T
A
) /
θ
JA
UNIT
V
V
V
V
V
V
°C
°C
°C
W
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating
Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3.2
THERMAL INFORMATION
THERMAL METRIC
(1)
TAS2521
RGE (24 PINS)
32.2
30.0
9.2
0.3
9.2
2.2
°C/W
UNITS
θ
JA
θ
JCtop
θ
JB
ψ
JT
ψ
JB
θ
JCbot
(1)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report,
SPRA953
4
ELECTRICAL SPECIFICATIONS
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TAS2521
www.ti.com
SLAS687A – FEBRUARY 2013 – REVISED FEBRUARY 2013
3.3
Recommended Operating Conditions
MIN
NOM
1.8
1.8
1.8
MAX
1.95
1.95
5.5
3.6
Ω
Ω
0.5
10
50
400
–40
85
V
RMS
kΩ
MHz
kHz
°C
V
UNIT
over operating free-air temperature range (unless otherwise noted)
AVDD
(1)
DVDD
SPKVDD
(1)
IOVDD
Speaker impedance
Headphone impedance
V
I
Analog audio full-scale input
voltage
Line output load impedance
(in half drive ability mode)
MCLK
(3)
SCL
T
A
(1)
(2)
(3)
Master clock frequency
SCL clock frequency
Operating free-air temperature
Referenced to AVSS
(2)
Referenced to DVSS
(2)
Referenced to SPKVSS
(2)
Referenced to IOVSS
(2)
Load applied across class-D output pins (BTL)
AC-coupled to R
L
AVDD = 1.8 V, single-ended
AC-coupled to R
L
IOVDD = DVDD = 1.8V
1.5
1.65
2.7
1.1
4
16
Power-supply voltage range
To minimize battery-current leakage, the SPKVDD voltage level should not be below the AVDD voltage level.
All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground
signals. By use of a wide trace or ground plane, ensure a low-impedance connection between AVSS and DVSS.
The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.
3.4
Electrical Characteristics
At 25°C, AVDD = 1.8V, IOVDD = 1.8 V, SPKVDD = 3.6 V, DVDD = 1.8 V, f
S
(audio) = 48 kHz, CODEC_CLKIN = 256 × f
S
,
PLL = Off
PARAMETER
INTERNAL OSCILLATOR—RC_CLK
Oscillator frequency
Audio DAC – Stereo Single-Ended Headphone Output
Load = 16Ω (single-ended), Input & Output CM =
0.9V, DOSR = 128, Device Setup MCLK = 256* fs,
Channel Gain = 0dB word length = 16 bits;
Processing Block = PRB_P1 Power Tune =
PTM_P3
0.5
Measured as idle-channel noise, A-weighted
(1)
0-dBFS input, 1-kHz input signal
Mute
Ripple on AVDD (1.8 V) = 200 mV
PP
at 1 kHz
–60dB 1kHz input full-scale signal
0dB, 1kHz input full scale signal
R
L
= 32
Ω,
THD+N
≤
–40 dB
R
L
= 16
Ω,
THD+N
≤
–40 dB
(1) (2)
(2)
TEST CONDITIONS
MIN
TYP
8.48
MAX
UNIT
MHz
Device Setup
Full-scale output voltage (0 dB)
ICN
THD+N
PSRR
DR
Idle channel noise
Total harmonic distortion + noise
Mute attenuation
Power-supply rejection ratio
(3)
Dynamic range, A-weighted
Gain error
P
O
(1)
(2)
(3)
Maximum output power
Vrms
μVms
dB
dB
dB
dB
mW
20.7
-78.2
103.7
47.2
88.1
±0.3
11
18
Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
DAC to headphone-out PSRR measurement is calculated as PSRR = 20 X log(∆V
HP
/
∆V
AVDD
).
Copyright © 2013, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
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