MODELS
SQSxxA
1
, SQSxxB, SSNxxA, SSNxxB,
SSWxxA, SSWxxB, SPDxxA, SPDxxB
Isolated and bussed circuits
Thin film resistor network
RoHS compliant available
FEATURES
Precision Nichrome Resistors on Silicon
Industry Standard Packaging
Ratio Tolerances
TCR Tracking Tolerances
Passivation coating provides protection in humid environments
JEDEC 95
< ± 0.05%
< ± 5 ppm/°C
SCHEMATICS
ELECTRICAL
2
Standard Resistance Range
3
Resistor Tolerances
Ratio Tolerances
TCR
Operating Temperature Range
Interlead Capacitance
Insulation Resistance
Maximum Operating Voltage
Noise, Maximum (MIL-STD-202, Method 308)
Resistor Power Rating at 70°C
1K ohms to 100K ohms (Isolated)
1K ohms to 30K ohms (Bussed)
± 0.25%
± 0.05%
Reference TCR table
-55°C to +125°C
< 2 pF
= 10,000 Megohms
100 Vdc or v PR
-25 dB
0.1 Watts
1
2
3
x
X
denotes package pin count. Reference package type section in this data sheet for description.
Specifications subject to change without notice.
E96 codes available.
BI Technologies Corporation
4200 Bonita Place
Fullerton, CA 92835 USA
Website:
www.bitechnologies.com
May 28, 2008
page 1 of 4
BI technologies
SQSxxA, SQSxxB, SSNxxA, SSNxxB,
SSWxxA, SSWxxB, SPDxxA, SPDxxB
PACKAGE POWER, WATTS @ 70°C
4
QSOP
16
0.6
20
0.7
24
0.8
8
0.4
SOIC (Narrow)
14
0.7
16
0.8
16
1.0
SOIC (Wide)
20
1.2
24
1.2
8
0.4
P-DIP
14
0.6
16
0.8
POWER DERATING CURVE
ENVIRONMENTAL (MIL-R-83401)
Thermal Shock plus Power Conditioning
Short Time Overload
Terminal Strength
Moisture Resistance
Mechanical Shock
Vibration
Low Temperature Operation
High Temperature Exposure
Resistance to Solder Heat
Marking Permanency
Flammability
Storage Temperature Range
∆R
0.25%
∆R
0.1%
∆R
0.1%
∆R
0.2%
∆R
0.25%
∆R
0.25%
∆R
0.05%
∆R
0.1%
∆R
0.1%
Per MIL-STD-202, Method 215
UL-94V-0 Rated
-55°C to +125°C
MECHANICAL
Lead Plating
Lead Material
Lead Configuration
Lead Coplanarity
Substrate Material
Resistor Material
Body Material
4
80/20 Tin Lead (Standard)
100 matte Tin (RoHS)
Copper Alloy
Gull Wing
0.004” (0.102 mm)
Silicon
Passivated Nichrome
Molded Epoxy
Maximum power per resistor @ 70°C is 100 mW, not to exceed package power.
BI Technologies Corporation
4200 Bonita Place
Fullerton, CA 92835 USA
Website:
www.bitechnologies.com
May 28, 2008
page 2 of 4
BI technologies
SQSxxA, SQSxxB, SSNxxA, SSNxxB,
SSWxxA, SSWxxB, SPDxxA, SPDxxB
ORDERING INFORMATION
5
S QS 16 A XXXX F S LF 13
Model Series:
S = Passivated Nichrome
on Silicon
Package Type:
Lead Count:
Circuit Type:
A=Isolated
B=Bussed
Resistance Code
Bulk packaging option:
7=7” Tape & Reel
13 = 13" Tap e & Reel
(No Code used for Tubes)
Lead Finish:
No Code=SnPb
LF=Lead Free (RoHS)
TCR Code
Tolerance Code
PACKAGE TYPE
Package Codes
QSOP
SOIC Narrow Body
SOIC Wide Body
P-DIP
QS
SN
SW
PD
Lead count
16, 20, 24
8, 14, 16
16, 20, 24
8, 14, 16
Mechanical Outline
MO-137
MS-012
MS-013
MS-001
RESISTANCE
5
First 3 digits are significant. Fourth digit denotes number of trailing zeros. For values less than 100, use “R” to denote a
decimal point. Example, 51 and 10000 ohms is coded as 51R0 and 1002 respectively. Standard values follow E96.
RESISTANCE TOLERANCE
Accuracy Code at 25°C
Absolute Resistance Tolerances (%)
Ratio Tolerances (R1 Ref) (%)
CA
± 0.25
± 0.05
CB
± 0.25
± 0.1
D
± 0.5
± 0.1
FA
± 1.0
± 0.05
F
± 1.0
± 1.0
G
± 2.0
N/A
J
± 5.0
N/A
TEMPERATURE COEFFICIENT OF RESISTANCE (TCR)
TCR Code (-55°C to 125°C)
Absolute (ppm/°C)
Tracking (R1 Ref) (ppm/°C)
Q
± 25
±5
P
± 50
±5
S
± 100
N/A
L
± 200
N/A
5
Contact customer service for custom designs and features.
BI Technologies Corporation
4200 Bonita Place
Fullerton, CA 92835 USA
Website:
www.bitechnologies.com
May 28, 2008
page 3 of 4
BI technologies
SQSxxA, SQSxxB, SSNxxA, SSNxxB,
SSWxxA, SSWxxB, SPDxxA, SPDxxB
BULK PACKAGING OPTIONS
Quantity
Model + Pin Count
SQS16
SQS20
SQS24
SSN08
SSN14
SSN16
SSW16
SSW20
SPD08
SPD14
SPD16
7” Reel
1000
1000
1000
1000
500
500
500
500
N/A
N/A
N/A
13” Reel
2500
2500
2500
2500
2500
2500
1500
1500
N/A
N/A
N/A
Tubes
100
50
50
100
50
50
50
38
50
25
25
TYPICAL MARKING
BI Technologies Corporation
4200 Bonita Place
Fullerton, CA 92835 USA
Website:
www.bitechnologies.com
May 28, 2008
page 4 of 4
BI technologies
FPGA/CPLD
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