TB6819FG
TOSHIBA BiCD Integrated Circuit
Silicon Monolithic
TB6819FG
Critical Conduction Mode (CRM) PFC Controller IC
Features
•
•
•
•
Operating voltage range: 10.0 V to 25 V
Startup voltage: 12.0 V (typ.)
Maximum drive current: 1.0 A
Variety of protection circuits
・DC
Input overvoltage protection (OVP-1)
・PFC
Output overvoltage protection (OVP-2)
・Undervoltage
lockout (UVLO)
・Open
feedback-loop detector (OFD)
・Brownout
protection (BOP)
SOP8-P-225-1.27
Weight: 0.08 g (typ.)
Block Diagram
GND
6
MULT
3
5
ZCD
4
IS
-
+
8
VCC
POUT
7
Q
Clamp
S
Timer1
Timer2
+
-
-
+
LLP
COMP
2
-
+
FB IN
1
+
-
-
+
OFD
MULT
R
QN
E-Amp
.
Brown-
out
BIAS
UVLO OVP-1
Internal circuit
OVP-2
.
COMP
1
2010-12-27
TB6819FG
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Supply voltage
Maximum input voltage on all pins
Minimum input voltage on all pins
Power dissipation 1 (Note 1)
Operating ambient temperature(Note 2)
Junction temperature
Storage temperature
Symbol
Vccmax
Vinmax
Vinmin
PDmax
Topr
Tj
Tstg
Rating
25.0
(Note 3)
GND - 0.3
650
-40 to 85
150
-55 to 150
Unit
V
V
V
mW
°C
°C
°C
Note 1: The rated power dissipation should be derated by ** mW/°C above Ta = 25°C ambient.
Note 2: Functional operation is guaranteed over the specified temperature range.
Note 3:
Pin No.
1
2
3
4
5
6
7
8
Pin Name
FBIN
COMP
MULT
IS
ZCD
GND
POUT
VCC
Maximum Input Voltage (Rating)
5.0
5.0
5.0
5.0
5.0
−
Do not apply any voltage.
25.0
Unit
V
Pin Assignments
FBIN
COMP
MULT
IS
1
2
3
4
8
7
6
5
Vcc
POUT
GND
ZCD
2
2010-12-27
TB6819FG
Pin Function
No.
Pin Name
Functional Description
Output voltage feedback pin. This is the input of the error amplifier (E-Amp), OVP-2 and OFD.
The PFC output voltage should be resistively divided down and applied to this pin. The error amplifier reference
voltage is set to 2.5 V (typ.). For other features, see the following.
1. Overvoltage protection on the PFC output (OVP-2)
1
FB IN
If the PFC output voltage increases and this pin voltage exceeds 2.7 V, the POUT (pin 7) output is forced to
Low. The POUT pin will then be enabled again when this pin voltage falls below 2.5 V.
2. Open-feedback detection (OFD)
If this pin voltage falls below 0.25 V due to error conditions such as an open-feedback loop, the POUT (pin 7)
output is forced to Low. The POUT pin will then be enabled again when this pin voltage reaches 0.5 V.
Error amplifier output.
2
COMP
An external filter is required to keep the open loop gain below 0 dB at the frequency twice the AC input
frequency that is superimposed on the PFC output. This external filter must be designed to provide an enough
phase margin.
Detection pin for a full-wave rectified AC voltage waveform. This pin is the input of the multiplier and BOP circuit.
The full-wave rectified voltage is resistively divided and connected to this pin.
3
MULT
The full-wave rectified voltage applied to this pin is internally multiplied to serve as a reference signal for the
PFC operation.
If the MULT voltage is below 0.75 V, the BOP is activated and the TB6819FG does not start remaining in
Standby mode. After the TB6819FG is started, it stops its operation and enters Standby mode if the MULT
voltage falls below 0.55 V and its peak voltage remains below 0.75 V for 100 ms.
Input pin for the current detection comparator. If the IS voltage exceeds the multiplier output voltage, which is
the IS comparator reference voltage, the RS flip-flop is reset. Too high a multiplier output voltage causes an
external switch to fail to switch off. To avoid this, the upper limit of the IS comparator reference voltage is
clamped to 1.7 V.
Zero current detection pin for an external transformer. The zero-current detector senses an inductor current via
the auxiliary winding of the coil and sets the RS flip-flop when the current reaches zero. Since the voltage of
auxiliary winding varies significantly, the ZCD pin has an internal clamp circuit.
If the inductor current does not reach zero for 200
μs
(typ.) while the TB6819FG is running, the Timer1 restart
timer output sets the RS flip-flop and restarts the switching.
6
7
8
GND
POUT
VCC
Ground pin.
Switching pulse output supplied to the FET switch.
Supply voltage input pin for the TB6819FG operation. The operating voltage ranges from 10 V (min) to 25 V
(max). Due to the UVLO feature, the TB6819FG is turned off when VCC falls below 9.5 V. The TB6819FG is
turned back on again when VCC reaches 12 V.
4
IS
5
ZCD
½Notes
when the protection circuits are working
The inner circuit works as following table when the protectors are going. Except for TSD, the output of pin 7 is kept low
level in order to shut down outer FET. Only the case of TSD, the output of pin 7 is kept floating. It is necessary to connect
pull down resistor indicated R15 to save outer FET when TSD works.
TSD is given to priority most. Even if the other protector is working, pin 7 would be floating if the IC temperature rise up
over 175
℃(typ.).
Protector
OVP-2
OFD
UVLO
Brown out
TSD
Remarks
FBIN≧Verr(2.5V)+180mV(typ.)
FBIN≦0.5V(typ.)
Vcc≦9.5V(typ.)
MULT≦0.75V(typ.)
Chip temperature≧175℃(typ.)
Inner circuit
Working
Working
Standby
Standby
Standby
Pin 7 output
L
L
L
L
Floating
3
2010-12-27
TB6819FG
Electrical Characteristics
(unless otherwise specified, VCC = 15 V, Ta = 25°C)
Characteristics
Supply voltage range
Current consumption
Startup current
Output pulse voltage
Output pulse rise time
Output pulse fall time
Input OVP voltage
Output OVP voltage
Symbol
VCC
ICC
Istart
VoH
VoL
TRPF
TSPF
V
OVP-1
V
OVP-2
75 KHz, 1000 pF
At startup
Output load current: 100 mA
Output load current: 100 mA
Load: 10
Ω,
1000 pF
Load: 10
Ω,
1000 pF
Self-limiting
Threshold voltage
(disables POUT)
Recovery threshold
Threshold voltage
(disables POUT)
Hysteresis
Shutdown threshold
Recovery threshold
Negative-going threshold
voltage
Hysteresis
Upper limit: 3 mA
Lower limit: -3 mA
―
Vcc-2.0
―
―
―
25
Verr+0.12
Verr-0.05
0.20
180
8.8
11.5
1.2
150
4
0.15
2.47
55
Source
Sink
Output voltage compensation
under light-load conditions
Upper limit of the IS reference
voltage
Including the RC time constant
for noise filtering
Timer1
FB IN = Open, sink current
Test
Circuit
Remarks
Min.
10
Typ.
15
4
72.5
―
―
25
10
27.5
Verr+0.18
Verr
0.25
230
9.5
12
1.4
300
5.5
0.5
2.52
90
-1
1
2.05
1.55
2.2
1.7
500
60
-1
200
―
400
1
1.5
1.5
Upper
Lower
G
MULT
*(COMP-2.5)*MULT = IS
COMP=3.5V MULT=2V-1V
Maximum MULT input voltage
Maximum COMP input voltage
Positive-going threshold voltage
(starts the IC)
Hysteresis
Brownout turn-on delay
tb
Id
source
Id sink
τ
IS
TSD
Timer3
2.55
2.1
-0.1
0.35
3.0
3.5
0.71
0.14
50
0.5
3.5
4.0
0.75
0.2
100
2.65
2.2
2.80
2.3
0.1
0.65
―
―
0.79
0.27
200
2.3
1.9
Max.
25
6.5
99
―
0.4
50
30
30
Verr+0.24
Verr+0.05
0.30
280
10.2
12.5
1.6
400
6
0.9
2.57
135
Unit
V
mA
μA
V
ns
ns
V
V
V
V
mV
V
V
mV
V
V
μS
mA
mA
V
V
ns
μs
μA
μs
μs
V
V
μA
−
V
V
V
V
ms
OFD trip threshold voltage
V
OFD
UVLO trip threshold voltage
V
UVLO
ZCD trip threshold voltage
V
ZCD
ZCD clamp voltage
E-Amp reference voltage
E-Amp mutual inductance
Maximum E-Amp current
LLP trip threshold voltage
IS pin reference voltage
IS rise time
Restart time
FBIN input current
OFD response time
Output OVP response time
Quick startup voltage
MULT input current
MULT gain
MULT input linear operation
range
Brownout threshold voltage
V
ZCDP
Verr
gm
Ie
source
Ie sink
VLLP
Vis
ti
t res
I
FBIN
½
OFD
t
OVP-2
Vqu
VqL
I
MULT
G
MULT
V
LM
V
LC
Vb
Designed values are indicated in following table, these are not tested at the shipping.
Maximum POUT current
RC time constant for noise
filtering
Thermal shutdown threshold
Source
Sink
Timer2, 40 kΩ//5 pF
Threshold temperature
Hysteresis
150
―
―
0.5
1.0
200
175
25
―
―
―
A
A
ns
°C
°C
4
2010-12-27
TB6819FG
Principle of Operation
I-in
AC IN
L1
C-in
V2
L2
PFCOUT
V1
I1
Switch
GND
MULT
6
3
5
ZCD
4
IS
-
+
ZCD-COMP
8
VCC
7
Q
POUT
GND
Clamp
Timer2
S
Timer1
COMP
2
-
+
FB IN
1
+
-
-
+
MULT
+ I-COMP
-
-
+
LLP
BIAS
UVLO
OVP-1
R
QN
E-Amp
Brownout
Internal circuit
OFD
OVP-2
COMP
(1) Boost Converter Operation
1. Switch: ON
→
The L1 current increases.
2. The L1 current reaches the I-COMP reference
current.
→
RS flip-flop is reset.
→
POUT toggles.
→
Switch goes off.
→
V1 toggles High.
→
V2 toggles High.
3. The L1 current decreases to zero.
→
The V1 and V2 voltages decrease rapidly.
4. The V2 voltage falls below the ZCD-COMP
reference voltage (1.4 V).
→
ZCD-COMP goes High.
→
RS flip-flop is set.
→
Switch goes on (Back to
step 1.)
PULSE
OUT
V1
I1
V2
I-COMP
OUT
ZCD-COMP
OUT
①
1
②
2
③④
3 4
I-in waveform: Ripple-current filtering using a capacitor C-in
I-in波½：コンデンサC-inによってリプル除去
I1 waveform
I1波½
(2) Power Factor Correction (Critical Conduction Mode)
a)Step 2 causes the I-COMP reference current signal to form
a sinusoidal waveform.
b) An envelope of the L1 current that flows upon resetting the
RS flip-flop to turn the Switch off forms a sinusoidal
waveform.
Waveforms of I-in and I1
I-in,I1波½
5
2010-12-27
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