LTC6954
Low Phase Noise,
Triple Output Clock
Distribution Divider/Driver
FEATURES
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DESCRIPTION
The
LTC
®
6954
is a family of very low phase noise clock
distribution parts. Each part has three outputs and each
output has an individually programmable frequency
divider and delay. There are four members of the family,
differing in their output logic signal type:
LTC6954-1:
Three LVPECL outputs
LTC6954-2:
Two LVPECL and one LVDS/CMOS outputs
LTC6954-3:
One LVPECL and two LVDS/CMOS outputs
LTC6954-4:
Three LVDS/CMOS outputs
Each output is individually programmable to divide the
input frequency by any integer from 1 to 63, and to delay
each output by 0 to 63 input clock cycles. The output duty
cycle is always 50%, regardless of the divide number.
The LVDS/CMOS outputs are jumper selectable via the
OUTxSEL pins to provide either an LVDS logic output or
a CMOS logic output.
The LTC6954 also features Linear Technology’s EZSync
system for perfect clock synchronization and alignment
every time.
All device settings are controlled through an SPI-compatible
serial port.
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Low Noise Clock Distribution: Suitable for High
Speed/High Resolution ADC Clocking
Additive Jitter < 20fs
RMS
(12kHz to 20MHz)
Additive Jitter < 85fs
RMS
(10Hz to Nyquist)
1.8GHz Maximum Input Frequency
(LTC6954-1 When DELAY = 0)
1.4GHz Maximum Input Frequency
(LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4)
EZSync™ Clock Synchronization Compatible
Three Independent, Low Noise Outputs
Four Output Combinations Available
Three Independent Programmable Dividers Covering
All Integers from 1 to 63
Three Independent Programmable Delays Covering
All Integers from 0 to 63
–40°C to 105°C Junction Temperature Range
APPLICATIONS
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Clocking High Speed, High Resolution ADCs, DACs
and Data Acquisition Systems
Low Jitter Clock Distribution
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 8319551, 8819472.
TYPICAL APPLICATION
0.1µF
UP TO 1.4GHz
49.9
49.9
SYNC
OUT0SEL
3.3V
OUT1SEL
OUT2SEL
SDO
SPI
SERIAL
PORT
SDI
SCLK
CS
GND
SERIAL
PORT
AND
DIGITAL
SYNC
CONTROL
IN
+
IN
–
49.9
DELAY
0 TO 63
DELAY
0 TO 63
DELAY
0 TO 63
DIVIDE
1 TO 63
DIVIDE
1 TO 63
DIVIDE
1 TO 63
V
+
LTC6954-3
LVPECL OUTPUT
FREQUENCY
UP TO 1.8GHz
LVDS OUTPUT
FREQUENCY
UP TO 1.4GHz
CMOS OUTPUT
FREQUENCY
UP TO 250MHz
3.3V
Additive Phase Noise vs Offset Frequency,
f
IN
= 622.08MHz, Mx[5:0] = 4,
f
OUTx
= 155.52MHz
–120
ADDITIVE PHASE NOISE (dBc/Hz)
–130
–140
–150
–160
–170
–180
6954 TA01a
OUT0
+
OUT0
–
OUT1
+
OUT1
–
OUT2
+
OUT2
–
10
100
1k
10k 100k
1M
OFFSET FREQUENCY (Hz)
10M
6954 TA01b
Rev. A
Document Feedback
For more information
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1
LTC6954
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW
OUT2SEL
OUT1SEL
TEMP
31
30 V
IN+
29 GND
28 IN
–
27 IN
+
26 GND
37
GND
25 V
IN+
24 V
A+
23 V
A+
22 SYNC
21 V
D+
20 SDI
19 SCLK
13
OUT0SEL
14
GND
15
V
A+
16
CS
17
SDO
18
V
D+
GND
GND
32
Supply Voltages
(V
A+
, V
D+
, V
IN+
, V
OUT0+
, V
OUT1+
and
V
OUT2+
to GND) ........................................................3.6V
LTC6954-1, -2, -3 LVPECL Outputs
OUTx Output Voltage High ......................V
OUT+
+ 0.3V
OUTx Output Voltage Low ..................... Source 25mA
LTC6954-2, -3, -4 LVDS/CMOS Outputs
OUTx ..........................................–0.3V to (V
A+
+0.3V)
TEMP Input Current ...............................................10mA
TEMP Low Voltage ................................................–0.3V
Voltage on All Other Pins .............. –0.3V to (V
A+
+ 0.3V)
Operating Junction Temperature Range, T
J
(Note 2)
LTC6954I ............................................... –40°C to 105°C
Junction Temperature, T
JMAX
................................ 150°C
Storage Temperature Range .................. –65°C to 150°C
36
V
OUT2+
1
OUT2
–
2
OUT2
+
3
V
OUT2+
4
V
OUT1+
5
OUT1
–
6
OUT1
+
7
V
OUT1+
8
V
OUT0+
9
OUT0
–
10
OUT0
+
11
V
OUT0+
12
35
V
A+
34
33
UFF PACKAGE
36-LEAD (4mm
×
7mm) PLASTIC QFN
0.5mm LEAD PITCH
T
JMAX
= 150°C,
θ
JCbottom
= 2°C/W,
θ
JCtop
= 18°C/W
EXPOSED PAD (PIN 37) IS GND, MUST BE SOLDERED TO PCB GND
ORDER INFORMATION
LEAD FREE FINISH
LTC6954IUFF-1#PBF
LTC6954IUFF-2#PBF
LTC6954IUFF-3#PBF
LTC6954IUFF-4#PBF
TAPE AND REEL
LTC6954IUFF-1#TRPBF
LTC6954IUFF-2#TRPBF
LTC6954IUFF-3#TRPBF
LTC6954IUFF-4#TRPBF
PART MARKING
69541
69542
69543
69544
PACKAGE DESCRIPTION
36-Lead (4mm × 7mm) Plastic QFN
36-Lead (4mm × 7mm) Plastic QFN
36-Lead (4mm × 7mm) Plastic QFN
36-Lead (4mm × 7mm) Plastic QFN
JUNCTION TEMPERATURE RANGE
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
–40°C to 105°C
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications.
Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. A
2
For more information
www.analog.com
LTC6954
The
l
denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at T
A
= 25°C. V
A+
= V
D+
= V
IN+
= V
OUT0+
= V
OUT1+
= V
OUT2+
= 3.3V, unless
otherwise specified. All voltages are with respect to GND. (Note 2)
SYMBOL
f
IN
V
IN
DC
IN
PARAMETER
Input Frequency
Input Signal Level
Input Slew Rate
Input Duty Cycle
Self-Bias Voltage
Minimum Common Mode Level
Maximum Common Mode Level
Input Resistance
Input Capacitance
Output Divider (M)
Mx[5:0]
DELx[5:0]
Divider Range
M0[5:0], M1[5:0], M2[5:0]
Divider Delay in Input Clock Cycles
DEL0[5:0], DEL1[5:0], DEL2[5:0]
Frequency
Differential Voltage
(Output Static)
Common Mode Voltage
(Output Static)
All Integers Included
All Integers Included
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ELECTRICAL CHARACTERISTICS
Input (IN
+
, IN
–
)
CONDITIONS
LTC6954-1, DELx = 0
LTC6954-1 (DELx > 0), LTC6954-2, -3, -4
Single-Ended
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MIN
TYP
MAX
1800
1400
UNITS
MHz
MHz
V
P-P
V/µs
%
0.2
100
0.8
50
1.5
1.9
2.05
1.8
2.3
2.2
V
V
V
400mV
P-P
Differential Input
400mV
P-P
Differential Input
Differential
Differential
1
0
l
1.8
2.2
0.5
2.7
kΩ
pF
63
63
Cycles
Cycles
LVPECL Clock Outputs
f
OUT
|V
OD
|
V
CM
LTC6954-1, DELx = 0
LTC6954-1 (DELx > 0), LTC6954-2, -3, -4
Single-Ended Termination = 50Ω to (V
OUTx+
– 2V)
Differential Termination = 100Ω, Internal Bias On
Single-Ended Termination = 50Ω to (V
OUTx+
– 2V)
Differential Termination = 100Ω, Internal Bias On
t
RISE
t
FALL
DC
LVPECL
Rise Time, 20% to 80%
Fall Time, 80% to 20%
Duty Cycle
Single-Ended Termination = 50Ω to (V
OUTx+
– 2V)
Differential Termination = 100Ω, Internal Bias On
Single-Ended Termination = 50Ω to (V
OUTx+
– 2V)
Differential Termination = 100Ω, Internal Bias On
Mx[5:0] = 1
Mx[5:0] > 1 (Even or Odd)
CMOS Clock Outputs
f
OUT
V
OH
V
OL
t
RISE
t
FALL
DC
CMOS
Frequency
High Voltage (Output Static)
Low Voltage (Output Static)
Rise Time, 20% to 80%
Fall Time, 80% to 20%
Duty Cycle
2.5mA Load
2.5mA Load
C
LOAD
= 2pF, CMSINV = 1
C
LOAD
= 2pF, CMSINV = 1
Mx[5:0] = 1
Mx[5:0] > 1 (Even or Odd)
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1800
1400
640
640
V
OUTx+
– 1.67
V
OUTx+
– 1.67
775
780
V
OUTx+
– 1.42
V
OUTx+
– 1.42
110
110
110
110
DC
IN
45
50
55
250
V
+
– 0.4
0.4
200
170
DC
IN
45
50
55
950
950
V
OUTx+
– 1.14
V
OUTx+
– 1.14
MHz
MHz
mV
PK
mV
PK
V
V
ps
ps
ps
ps
%
%
MHz
V
V
ps
ps
%
%
Rev. A
For more information
www.analog.com
3
LTC6954
The
l
denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at T
A
= 25°C. V
A+
= V
D+
= V
IN+
= V
OUT0+
= V
OUT1+
= V
OUT2+
= 3.3V, unless
otherwise specified. All voltages are with respect to GND. (Note 2)
SYMBOL
f
OUT
|V
OD
|
|ΔV
OD
|
V
OS
|ΔV
OS
|
t
RISE
t
FALL
|I
SA
|, |I
SB
|
|I
SAB
|
DC
LVDS
PARAMETER
Frequency
Differential Voltage
(Output Static)
Delta V
OD
(Output Static)
Offset Voltage (Output Static)
Delta V
OS
(Output Static)
Rise Time, 20% to 80%
Fall Time, 80% to 20%
Short-Circuit Current to Common
Short-Circuit Current to
Complementary
Duty Cycle
CONDITIONS
Differential Termination = 100Ω, 3.5mA Mode
Differential Termination = 50Ω, 7mA Mode
Differential Termination = 100Ω, 3.5mA Mode
Differential Termination = 50Ω, 7mA Mode
Differential Termination = 100Ω, 3.5mA Mode
Differential Termination = 50Ω, 7mA Mode
Differential Termination = 100Ω, 3.5mA Mode
Differential Termination = 50Ω, 7mA Mode
Differential Termination = 100Ω, 3.5mA Mode
Differential Termination = 50Ω, 7mA Mode
Differential Termination = 100Ω, 3.5mA Mode
Differential Termination = 50Ω, 7mA Mode
Differential Termination = 100Ω, 3.5mA Mode
Differential Termination = 50Ω, 7mA Mode
Shorted to GND, 3.5mA Mode
Shorted to GND, 7mA Mode
3.5mA Mode
7mA Mode
Mx[5:0] = 1
Mx[5:0] > 1 (Even or Odd)
Output Propagation Delays
t
PD(LVPECL)
Propagation Delay From IN to
Any LVPECL Output
Temperature Variation of the
Propagation Delay From IN to
Any LVPECL Output
t
PD(LVDS)
Propagation Delay From IN to
Any LVDS Output,
LVCSx = 1 (7mA Mode)
Temperature Variation of the
Propagation Delay From IN to
Any LVDS Output,
LVCSx = 1 (7mA Mode)
Propagation Delay From IN to
Any LVDS Output,
LVCSx = 0 (3.5mA Mode)
Temperature Variation of the
Propagation Delay From IN to
Any LVDS Output,
LVCSx = 0 (3.5mA Mode)
t
PD(CMOS)
Propagation Delay From IN to
Any CMOS Output, Complementary
Outputs (CMSINVx = 1)
Temperature Variation of the
Propagation Delay From IN to
Any CMOS Output (CMSINVx = 1)
Mx[5:0] = 1
Mx[5:0] > 1
Mx[5:0] = 1
Mx[5:0] > 1
Mx[5:0] = 1
Mx[5:0] > 1
Mx[5:0] = 1
Mx[5:0] > 1
Mx[5:0] = 1
Mx[5:0] > 1
Mx[5:0] = 1
Mx[5:0] > 1
Mx[5:0] = 1
Mx[5:0] > 1
Mx[5:0] = 1
Mx[5:0] > 1
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ELECTRICAL CHARACTERISTICS
MIN
TYP
MAX
800
1400
UNITS
MHz
MHz
mV
PK
mV
PK
mV
mV
V
V
mV
mV
ps
ps
ps
ps
mA
mA
mA
mA
%
LVDS Clock Outputs
290
290
–30
–30
1.16
1.15
–15
–15
370
370
450
450
30
30
1.23
1.23
1.32
1.32
15
15
240
120
240
120
16
25
4
8
DC
IN
45
250
320
50
360
430
0.65
0.68
305
370
420
480
0.8
0.85
480
550
0.8
0.85
1.25
1.32
1.3
1.4
545
625
55
480
550
%
ps
ps
ps/°C
ps/°C
ps
ps
ps/°C
ps/°C
ps
ps
ps/°C
ps/°C
ns
ns
ps/°C
ps/°C
Rev. A
4
For more information
www.analog.com
LTC6954
The
l
denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at T
A
= 25°C. V
A+
= V
D+
= V
IN+
= V
OUT0+
= V
OUT1+
= V
OUT2+
= 3.3V, unless
otherwise specified. All voltages are with respect to GND. (Note 2)
SYMBOL
PARAMETER
Skew: Any LVPECL Output to
Any LVPECL Output
Skew: Any LVPECL Output to
Any LVDS Output
Skew: Any LVPECL Output to
Any LVDS Output
Skew: Any LVPECL Output to
Any CMOS Output
Skew: Any LVDS Output to
Any LVDS Output
t
SKEW
Skew: Any LVDS Output to
Any LVDS Output
CONDITIONS
Mx[5:0], My[5:0] Both = 1 or Both > 1
IBIASx = 0 or 1
M
LVPECL
[5:0], M
LVDS
[5:0] Both = 1 or Both > 1
IBIASx = 0 or 1, LVCSy = 1
M
LVPECL
[5:0] = M
LVDS
[5:0] = 1 or Both > 1
IBIASx = 0 or 1, LVCSx = 0
M
LVPECL
[5:0], M
CMOS
[5:0] Both = 1 or Both > 1
IBIASx = 0 or 1, CMSINVy = 1
Mx[5:0], My[5:0] Both = 1 or Both > 1
LVCSx = 1 for Both Outputs
Mx[5:0], My[5:0] Both = 1 or Both > 1
LVCSx = 0 for Both Outputs
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ELECTRICAL CHARACTERISTICS
Output Skews
MIN
–50
TYP
MAX
50
UNITS
ps
ps
ps
ps
65
120
875
–50
5
50
800
5
30
50
ps
ps
ps
ps
ps
ps
Skew: Any LVDS Output (LVCSx = 1) to Mx[5:0], My[5:0] Both = 1 or Both > 1
LVCSx = 1, LVCSy = 0
Any LVDS Output (LVCSy = 0)
Skew: Any LVDS Output to
Any CMOS Output
Skew: Any CMOS Output to
Any CMOS Output
Skew: Any CMOS Output to
Any CMOS Output, the First Output is
Complementary, the Second Output is
In-Phase
Additional Skew: Any Output to Any
Output, Dividers Not the Same
M
LVDS
[5:0], M
CMOS
[5:0] Both = 1 or Both > 1
LVCSx = 1, CMSINV = 1
Mx[5:0], My[5:0] Both = 1 or Both > 1
CMSINV = 1
CMSINVx = 1, CMSINVy = 0
Mx[5:0] = 1, My[5:0] > 1
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35
70
120
ps
Rev. A
For more information
www.analog.com
5
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