into signals that are transmitted across an isolation barrier
to another LTC4310. The receiving LTC4310 decodes the
transmission and drives its l
2
C bus to the appropriate logic
state. The isolation barrier can be bridged by an inexpensive
Ethernet, or other transformer, to achieve communications
across voltage differences reaching thousands of volts, or
it can be bridged by capacitors for lower voltage isolation.
The LTC4310-1 is intended for use in 100kHz I
2
C systems.
The LTC4310-2 is intended for 400kHz I
2
C systems.
Rise time accelerators provide strong pull-up currents on
SCL and SDA rising edges to meet rise time specifications
for heavily loaded systems. Data and clock Hot Swap™
circuitry prevent data corruption when a card is inserted
into or removed from a live bus. When a bus is stuck low
for 37ms, the LTC4310 turns off its pull-down devices
and generates up to sixteen clocks and a STOP bit in an
attempt to free the bus. Driving EN low sets the LTC4310
in a very low current shutdown mode to conserve power.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
n
n
n
n
n
n
n
n
n
n
Bidirectional I
2
C Communication Between Two
Isolated Buses
Full Isolation with Inexpensive Ethernet
Transformers or Capacitors
Low Voltage Level Shifting
I
2
C Maximum Operating Frequency:
100kHz for LTC4310-1
400kHz for LTC4310-2
I
2
C Specification Compliant V
OL
, V
IL
±5kV Human Body Model ESD Protection
Rise Time Accelerators
SDA, SCL Hot-Swapping
Very Low Shutdown Current
Stuck Bus Disconnect and Recovery
Thermal Shutdown
10-Lead MSOP and 3mm
×
3mm DFN Packages
Isolated I
2
C, SMBus and PMBus Interfaces
Isolated Power Supplies
Positive-to-Negative Rail Communications
Power-over-Ethernet
applicaTions
n
n
n
n
Typical applicaTion
1500V Isolated I
2
C System
3.3V
0.01µF
10/100Base-TX
ETHERNET TRANSFORMER
VCC TXP
RXP
VCC
0.01µF
ISOLATED
5V
SCL
SDA
LTC4310 Operating Through
20kV/µs Common Mode Transient
3.3k
3.3k
LTC4310-1
SDA
SCL
EN
READY
GND RXN
EPF8119S
0.01µF
TXN
RXP
0.01µF
LTC4310-1
RXN
TXP
SDA
SCL
EN
READY
TXN GND
3.3k
3.3k
0V
2V/DIV
SDA1
SCL1
SDA2
SCL2
20kV/µs
0V
2µs/DIV
431012 TA01a
431012 TA01b
500V/
DIV
431012fa
1
LTC4310-1/LTC4310-2
absoluTe MaxiMuM raTings
(Notes 1, 4)
Input Supply Voltage (V
CC
) .......................... –0.3V to 6V
Input and Bidirectional Pin Voltages
SCL, SDA, EN, RXP RXN.......................... –0.3V to 6V
,
Output Voltages
READY
..................................................... –0.3V to 6V
TXP TXN ...................... –0.3V to V
CC
+ 0.3V (6V Max)
,
Maximum Sink Current (SDA, SCL,
READY)
..........30mA
Operating Ambient Temperature Range
LTC4310C ................................................ 0°C to 70°C
LTC4310I.............................................. –40°C to 85°C
Storage Temperature Range
DD ..................................................... –65°C to 125°C
MS ..................................................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS Package ...................................................... 300°C
pin conFiguraTion
TOP VIEW
EN
SDA
SCL
READY
GND
1
2
3
4
5
11
GND
10 RXN
9 RXP
8 V
CC
7 TXP
6 TXN
EN
SDA
SCL
READY
GND
1
2
3
4
5
TOP VIEW
10
9
8
7
6
RXN
RXP
V
CC
TXP
TXN
DD PACKAGE
10-LEAD (3mm
×
3mm) PLASTIC DFN
T
JMAX
= 125°C,
θ
JA
= 43°C/W
EXPOSED PAD (PIN 11) PCB CONNECTION TO GROUND IS OPTIONAL
MS PACKAGE
10-LEAD PLASTIC MSOP
T
JMAX
= 150°C,
θ
JA
= 120°C/W
orDer inForMaTion
LEAD FREE FINISH
LTC4310CDD-1#PBF
LTC4310IDD-1#PBF
LTC4310CMS-1#PBF
LTC4310IMS-1#PBF
LTC4310CDD-2#PBF
LTC4310IDD-2#PBF
LTC4310CMS-2#PBF
LTC4310IMS-2#PBF
TAPE AND REEL
LTC4310CDD-1#TRPBF
LTC4310IDD-1#TRPBF
LTC4310CMS-1#TRPBF
LTC4310IMS-1#TRPBF
LTC4310CDD-2#TRPBF
LTC4310IDD-2#TRPBF
LTC4310CMS-2#TRPBF
LTC4310IMS-2#TRPBF
PART MARKING*
LFCH
LFCH
LTFCG
LTFCG
LFCK
LFCK
LTFCJ
LTFCJ
PACKAGE DESCRIPTION
10-Lead (3mm
×
3mm) Plastic DFN
10-Lead (3mm
×
3mm) Plastic DFN
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead (3mm
×
3mm) Plastic DFN
10-Lead (3mm
×
3mm) Plastic DFN
10-Lead Plastic MSOP
10-Lead Plastic MSOP
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
431012fa
2
LTC4310-1/LTC4310-2
elecTrical characTerisTics
SYMBOL
Supplies
V
CC
I
CC
I
CC(SD)
V
CCH(UVL)
V
CC(UVL, HYST)
I
2
C Interface
V
SDA,SCL(OL)
V
SDA,SCL(IL,R)
V
SDA,SCL(IL,F)
I
SDA,SCL(OH)
dV/dt
RISE
SDA, SCL Logic Low Output Voltage
I
(SDA,SCL)
= 4mA, 500µA; V
CC
= 3V, 5.5V
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 3.3V, unless otherwise noted.
PARAMETER
Input Supply Range
Input Supply Current, LTC4310-1
Input Supply Current, LTC4310-2
Shutdown Input Supply Current
Input Supply Undervoltage Lockout
Rising Threshold Voltage
Input Supply Undervoltage Lockout
Hysteresis
EN = V
CC
= 5.5V, SDA = SCL = V
SDA,SCL(OL)
EN = V
CC
= 5.5V, SDA = SCL = V
SDA,SCL(OL)
EN = 0V, V
CC
= 5.5V
CONDITIONS
l
l
l
l
l
l
MIN
3
TYP
MAX
5.5
UNITS
V
mA
mA
µA
V
mV
6.5
7
0.1
2.1
90
2.4
190
8
8.5
±10
2.7
270
310
0.3 • V
CC
0.4 • V
CC
350
0.35 • V
CC
0.45 • V
CC
0
380
0.4 • V
CC
0.5 • V
CC
±5
1.4
2.6
3.9
6.9
270
mV
V
V
µA
V/µs
V/µs
V/µs
V/µs
ns
kHz
kHz
SDA, SCL Controlled Rising Edge Rate V
CC
= 3V, 5.5V (Note 5)
Turn-Off Threshold Voltage
SDA, SCL Logic Low Falling Input
Threshold Voltage
SDA, SCL Input Current
Bus Line Controlled Rising Edge Rate,
LTC4310-1
Bus Line Controlled Rising Edge Rate,
LTC4310-2
V
CC
= 3V
SDA = SCL = 5.5V; V
CC
= 0V, 5.5V
0.35V < V
BUS
< 0.35 • V
CC
, V
CC
= 3V
0.35V < V
BUS
< 0.35 • V
CC
, V
CC
= 5.5V
0.35V < V
BUS
< 0.35 • V
CC
, V
CC
= 3V
0.35V < V
BUS
< 0.35 • V
CC
, V
CC
= 5.5V
V
CC
= 5.5V (Note 3)
LTC4310-1
LTC4310-2
SCL, SDA = V
CC
(Note 2)
V
CC
= 3V (Note 5)
V
CC
= 3V
I
2
C Interface Timing
l
l
l
l
l
l
l
0.8
1.5
2
3.9
1.16
2.14
3
5.4
170
t
PHL(SDA,SCL)
f
SCL(MAX)
C
IN
V
BOOST
I
BOOST
SDA, SCL High-to-Low Propagation
Delay
Maximum SCL Clock Frequency
SCL, SDA Input Capacitance
SDA, SCL Rise Time Accelerator
Activation Threshold Voltage
SDA, SCL Rise Time Accelerator
Current
READY
Output Low Voltage
READY
Off-Current
EN Rising Threshold Voltage
EN Falling Threshold Voltage
EN Input Current
Bus Idle Time
Start-Up Filter Time
SDA, SCL Bus Stuck Low Disconnect
100
400
10
pF
V
mA
Rise Time Accelerators
l
l
0.32 • V
CC
0.45 • V
CC
2
6
0.5 • V
CC
READY
Open-Drain Output
V
READY(OL)
I
READY(OH)
V
EN,RISE
V
EN,FALL
I
EN(OH)
t
IDLE
t
UVLO,EN_FILT
t
STUCK
I
READY
= 4mA
READY=
V
CC
= 5.5V, EN = 0V
l
l
50
0.1
0.6 • V
CC
0.1 • V
CC
75
700
27
0.3 • V
CC
0.1
115
900
37
400
±10
0.9 • V
CC
±10
155
1200
47
mV
µA
V
V
µA
µs
µs
ms
Connection Control
l
l
EN = V
CC
= 5.5V
l
l
l
l
431012fa
3
LTC4310-1/LTC4310-2
elecTrical characTerisTics
SYMBOL
t
MAX(TX)
t
MAX(RX)
Transmit Outputs
V
TX(OL)
V
TX(OH)
t
R(TX)
t
F(TX)
t
PWMIN(TX)
Receive Inputs
V
RX(TH)
t
PWMIN(RX)
R
RX(IN)
RXP RXN Differential High Level
,
Threshold
RXP RXN Minimum Received Pulse
,
Width
RXP RXN Differential Input Resistance
,
RXP RXN Pins; V
CC
= 3V, 5.5V
,
V
CC
= 3V, 5.5V
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 3.3V, unless otherwise noted.
PARAMETER
Maximum Time Between TXP TXN
,
Transmit Events
Maximum Time Between RXP RXN
,
Receive Events
TXP TXN Single-Ended Output Low
,
TXP TXN Single-Ended Output High
,
TXP TXN Output Rise Time
,
TXP TXN Output Fall Time
,
TXP TXN Minimum Transmission
,
Pulse Width
I
SINK
= 100µA, V
CC
= 3V
15kΩ to GND on TXP TXN; V
CC
= 3V, 5.5V
,
C
TXP
, C
TXN
= 20pF
C
TXP
, C
TXN
= 20pF
V
CC
= 3V, 5.5V
CONDITIONS
l
l
MIN
0.85
3.4
TYP
1.15
4.6
MAX
1.45
5.8
UNITS
ms
ms
l
l
l
l
l
1.5
0.95
1.25
1
1
31.5
35
5
1.52
3
3
39
mV
V
ns
ns
ns
0.3
30
13
0.5
0.875
V
ns
16.5
20
kΩ
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2.
Guaranteed by design, not tested in production.
Note 3.
SDA, SCL high-to-low propagation delay is measured from the
beginning of a new received message telling the LTC4310 to drive its SDA,
SCL pins from high to low, to when the SDA, SCL lines have fallen below
0.5 • V
CC
. It includes approximately 87ns required for an LTC4310 to
receive a message on the RXP and RXN pins, plus the time the LTC4310
requires to process the message and pass the low to the data and clock
buffers, plus the time required by the buffers to drive their bus pins below
0.5 • V
CC
.
Note 4.
All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 5.
Internal control circuitry prevents the rise time accelerators from
activating until the rising edge rate control circuitry is off.
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
