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LTC2195IUKG#TRPBF

产品描述2-Channel Dual ADC Pipelined 125Msps 16-bit Serial Automotive 52-Pin QFN EP T/R
文件大小860KB,共28页
制造商ADI(亚德诺半导体)
官网地址https://www.analog.com
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LTC2195IUKG#TRPBF概述

2-Channel Dual ADC Pipelined 125Msps 16-bit Serial Automotive 52-Pin QFN EP T/R

LTC2195IUKG#TRPBF规格参数

参数名称属性值
欧盟限制某些有害物质的使用Compliant
ECCN (US)3A001.a.5.a.5
Part StatusActive
HTS8542.39.00.01
Converter TypeGeneral Purpose
ArchitecturePipelined
Resolution16bit
Number of ADCs2
Number of Input Channels2
Sampling Rate125Msps
Digital Interface TypeSerial|LVDS
Input TypeVoltage
Input Signal TypeSingle-Ended|Differential
Voltage ReferenceInternal|External
Voltage Supply SourceSingle
Input Voltage1Vp-p/2Vp-p
Minimum Single Supply Voltage (V)1.7
Typical Single Supply Voltage (V)1.8
Maximum Single Supply Voltage (V)1.9
Typical Power Dissipation (mW)479
Maximum Power Dissipation (mW)535
Integral Nonlinearity Error±7LSB
Full Scale Error-2/0.6%FSR
Signal to Noise Ratio76.8dBFS(Typ)
No Missing Codes (bit)16
Sample and HoldYes
Single-Ended InputYes
Digital Supply SupportNo
Minimum Operating Temperature (°C)-40
Maximum Operating Temperature (°C)85
系列
Packaging
Tape and Reel
Supplier PackageQFN EP
Pin Count52
Standard Package NameQFN
MountingSurface Mount
Package Height0.75(Max)
Package Length8
Package Width7
PCB changed52
Lead ShapeNo Lead

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LTC2195
LTC2194/LTC2193
16-Bit, 125/105/80Msps
Low Power Dual ADCs
FEATURES
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DESCRIPTION
The LTC
®
2195/LTC2194/LTC2193 are 2-channel, simul-
taneous sampling 16-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 76.8dB SNR and
90dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.07ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.4LSB
RMS
.
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs two bits or four bits
at a time. At lower sampling rates there is a one bit per
channel option. The LVDS drivers have optional internal
termination and adjustable output levels to ensure clean
signal integrity.
The ENC
+
and ENC
inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An internal clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
2-Channel Simultaneous Sampling ADC
Serial LVDS Outputs: 1, 2 or 4 Bits per Channel
76.8dB SNR
90dB SFDR
Low Power: 432mW/360mW/249mW Total
216mW/180mW/125mW per Channel
Single 1.8V Supply
Selectable Input Ranges: 1V
P-P
to 2V
P-P
550MHz Full-Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
52-Pin (7mm
×
8mm) QFN Package
APPLICATIONS
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Communications
Cellular Base Stations
Software-Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
TYPICAL APPLICATION
2-Tone FFT, f
IN
= 70MHz and 69MHz
1.8V
V
DD
CH1
ANALOG
INPUT
CH2
ANALOG
INPUT
ENCODE
INPUT
S/H
16-BIT
ADC CORE
16-BIT
ADC CORE
1.8V
OV
DD
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
0
–10
–20
–30
AMPLITUDE (dBFS)
–40
–50
–60
–70
–80
S/H
DATA
SERIALIZER
SERIALIZED
LVDS
OUTPUTS
PLL
–90
–100
–110
–120
GND
OGND
219543 TA01a
0
10
20
30
40
FREQUENCY (MHz)
50
60
219543
TA01b
219543f
1

 
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