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LTC2151IUJ-14#PBF

产品描述1-Channel Single ADC Pipelined 210Msps 14-bit Parallel/Serial (SPI)/LVDS 40-Pin QFN EP Tube
文件大小1MB,共32页
制造商ADI(亚德诺半导体)
官网地址https://www.analog.com
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LTC2151IUJ-14#PBF概述

1-Channel Single ADC Pipelined 210Msps 14-bit Parallel/Serial (SPI)/LVDS 40-Pin QFN EP Tube

LTC2151IUJ-14#PBF规格参数

参数名称属性值
欧盟限制某些有害物质的使用Compliant
ECCN (US)3A991c.3.
Part StatusActive
HTS8542.39.00.01
Converter TypeGeneral Purpose
ArchitecturePipelined
Resolution14bit
Number of ADCs1
Number of Input Channels1
Sampling Rate210Msps
Digital Interface TypeParallel|LVDS
Input TypeVoltage
Input Signal TypeDifferential
Voltage ReferenceInternal|External
Voltage Supply SourceSingle
Input Voltage1.5Vp-p
Minimum Single Supply Voltage (V)1.7
Typical Single Supply Voltage (V)1.8
Maximum Single Supply Voltage (V)1.9
Typical Power Dissipation (mW)374
Maximum Power Dissipation (mW)414
Integral Nonlinearity Error±5.1LSB
Full Scale Error-4/3%FSR
Signal to Noise Ratio70dBFS(Typ)
No Missing Codes (bit)14
Sample and HoldYes
Single-Ended InputNo
Digital Supply SupportNo
Minimum Operating Temperature (°C)-40
Maximum Operating Temperature (°C)85
系列
Packaging
Tube
Supplier Temperature GradeIndustrial
Supplier PackageQFN EP
Pin Count40
Standard Package NameQFN
MountingSurface Mount
Package Height0.75(Max)
Package Length6
Package Width6
PCB changed40
Lead ShapeNo Lead

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LTC2152-14/
LTC2151-14/LTC2150-14
14-Bit 250Msps/
210Msps/170Msps ADCs
FEATURES
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DESCRIPTION
The
LTC
®
2152-14/LTC2151-14/LTC2150-14
are 250Msps/
210Msps/170Msps 14-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 70dB SNR and
90dB spurious free dynamic range (SFDR). The 1.25GHz
input bandwidth allows the ADC to undersample high
frequencies with good performance. The latency is only
six clock cycles.
DC specs include ±0.85LSB INL (typ), ±0.25LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.82LSB
RMS
.
The digital outputs are double-data rate (DDR) LVDS.
The ENC
+
and ENC
inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
70dB SNR
90dB SFDR
Low Power: 356mW/338mW/313mW Total
Single 1.8V Supply
DDR LVDS Outputs
Easy-to-Drive 1.5V
P-P
Input Range
1.25GHz Full Power Bandwidth S/H
Optional Clock Duty Cycle Stabilizer
Low Power Sleep and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 12-Bit Versions
40-Pin (6mm × 6mm) QFN Package
Communications
Cellular Basestations
Software Defined Radios
Medical Imaging
High Definition Video
Testing and Measurement Instruments
APPLICATIONS
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TYPICAL APPLICATION
V
DD
OV
DD
D12_13
D0_1
LTC2152-14: 32K Point FFT,
f
IN
= 15MHz, –1dBFS, 250Msps
0
–20
AMPLITUDE (dBFS)
DDR
LVDS
–40
–60
–80
ANALOG
INPUT
S/H
14-BIT
PIPELINED
ADC
CORRECTION
LOGIC
OUTPUT
DRIVERS
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
21521014 TA01a
OGND
–100
–120
0
20
40
60
80
100
FREQUENCY (MHz)
120
21521014 TA01b
21521014fa
For more information
www.linear.com/LTC2152-14
1

 
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