NT3966
TFT LCD Source Driver
Features
n
Output : 420 output channels
n
6-bit resolution /64 gray scale
n
Dot inversion with polarity control
n
V1 ~ V10 for adjusting Gamma correction
n
Power for analog circuit : 6.5 ~ 10 V
n
Output dynamic range : 0.1 ~ AV
DD
-0.1V
n
Power consumption of analog circuit : 3mA
General Description
The NT3966 is a data driver IC for a color TFT LCD panel, SXGA+(1400*1050) applications. For better performance, dot
inversion and a wide range voltage output have been designed into this chip, and for reducing EMI, data inversion control has
been incorporated. This chip supplies 10 sections of voltage-reference for Gamma correction.
n
Power for interface circuit : 2.5~3.6V
n
Operating frequency : 65MHz
n
Output deviation : 10 ~ 20mV
n
Data inversion for reducing EMI
n
Cascade function with bi-direction shift control
n
CMOS silicon gate ( p-type substrate )
n
TCP package
Block diagram
OUT1
OUT2
OUT3
OUT420
OUT419
Out Driver Buffer ( 420 channels )
V1 ~ V10
10
Digit to Analog Converter
6
6
6
6
6
POL
REV1
D00 ~ D05
D10 ~ D15
D20 ~ D25
D30 ~ D35
D40 ~ D45
D50 ~ D55
Level Shift
6
6
6
6
6
6
Decoder
1
64
6
Decoder
18
6
6
6
6
Line Latch ( 420 X 6 bits X 2 )
18
LD
REV2
DIO1
70-bit Shift Register
DIO2
Vcc
GND
AVDD
AVSS
CLK
SHL
Version 1.0
1
DEC 7 ,2001
NT3966
TFT LCD Source Driver
P
in Description
Designation
D05 ~ D00
D15 ~ D10
D25 ~ D20
D35 ~ D30
D45 ~ D40
D55 ~ D50
REV1
REV2
CLK
V1 ~ V10
OUT1 ~
OUT420
SHL
I/O
I
Description
Data input. For six 6-bit data,2 pixels, of color data (R, G, B)
DX5 : MSB; DX0 : LSB
I
I
I
I
O
I
Controls whether the data of D00~D25 are inverted or not.
When “REV1”=1 these data will be inverted. EX. “00”
à
“ 3F”, “07”à “ 38”, “15”à “2A”, and so on.
Controls whether the data of D30~D55 are inverted or not, same as REV1.
Clock input; latching data onto the line latches at the rising edge.
Gamma correction reference voltage. The voltage of these pins must be AVSS< V10< V9<
V8<V7<V6; V5<V4<V3<V2<V1< AVDD
Output drive signals;
DIO1
DIO2
LD
POL
AV
DD
AVSS
Vcc
GND
Selects left or right shift;
SHL=“1” : DIO1
→OUT1,2,3,4,5,6→OUT7,8,9,10,11,12--→OUT415,416,417,418,419,420=
DIO2
SHL=“0” : DIO1=OUT1,2,3,4,5,6←OUT7,8,9,10,11,12←-- OUT415,416,417,418,419,420←DIO2
SHL
DIO1
DIO2
SHIFT
1
Input
Output
Right
0
Output
Input
Left
I/O Start pulse signal input/output
When SHL is applied high (SHL="1"), a start high-pulse on DIO1 is latched at the rising edge of the
CLK. Then the data are latched serially onto internal latches at the rising edge of the CLK. After all
line latches are filled with data, 70 clocks, a pulse is shifted out through the DIO2 pin at the rising
edge of the CLK. This function can cascade two or more devices for dot-size expansion. In normal
applications, the DIO2 signal of the first device is connected to the DIO1 of the second stage, the
DIO2 of the second one is connected to the DIO1 of the third, and so on, in a chain.
In contrast, when SHL is applied low, a start pulse inputs on DIO2, and a pulse outputs through
DIO1.
*Remark: The input pulse-width of DIO1/2 may exceed 1 clock-cycle.
I Latches the polarity of outputs and switches the new data to outputs.
1. At the rising edge, the pin latches the “POL” signal to control the polarity of the outputs.
2. The pin also controls the switch of the line registers that switches the new incoming data
to outputs.
*Remark: The LD may switch the new data to outputs at anytime even if the line data are not
completely full.
I Polarity selector for the dot-inversion control. Available at the rising edge of LD
“POL” value is latched at the rising edge of “LD” to control the polarity of the even or odd outputs.
“POL=1” indicates that even outputs are of positive polarity with a voltage range from V1~V5, and
odd outputs are of negative polarity with a voltage range from V6 to V10. On the other hand, if LD
receives low level “POL”, even outputs are of negative polarity and odd outputs are of positive
polarity.
POL=1: Even outputs range from V1 ~ V5
Odd outputs range from V6 ~ V10
POL=0: Even outputs range from V6 ~ V10
Odd outputs range from V1 ~ V5
I Power supply for analog circuit
I Ground pin for analog circuit
I Power supply for digital circuit
I Ground pin for digital circuit
Version 1.0
3
DEC 7 ,2001
NT3966
TFT LCD Source Driver
Power on/off sequence:
This IC is a high-voltage LCD driver, so it may be damaged by a large current flow when an incorrect power sequence is used.
The recommended sequence should be: digital power (Vcc&GND)è logic signals
èanalog
power (AVDD&AVSS)
èGamma
correction reference voltage(V1~V10). Reverse this sequence to shut down, or turn off all signals and power simultaneously.
Relationship between the order of input data and output channels
(1) SHL=”1”, Start pulse from DIO1, shift right
Output
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
Order
First data
Data
D05~D00 D15~D10 D25~D20 D35~D30 D45~D40 D55~D50
(2) SHL=”0”, Start pulse from DIO2, shift left
Output
OUT415 OUT416 OUT417 OUT418 OUT419 OUT420
Order
First data
Data
D05~D00 D15~D10 D25~D20 D35~D30 D45~D40 D55~D50
- --
--à
- --
- --
--à
- --
OUT420
Last data
D55~D50
OUT6
Last data
D55~D50
Relationship between input data and output voltage
The figure below shows the relationship among the input data and the output voltage and the polarity. The range of V1~V5 is
for positive polarity, and V6 ~ V10 for negative polarity. Please refer to the following page to get the relative resistor value and
voltage calculation method.
Gamma correction diagram
Vout
AVDD
V1
V2
V3
V4
V5
Vcom
V6
V7
V8
Negative polarity
V9
Positive polarity
V10
AVSS
00H
08H
10H
18H
20H
28H
30H
38H
3FH
Input Data
Remark: AV
DD
-0.1 > V1 > V2 > V3 > V4 > V5; V6 > V7 > V8 > V9 > V10 >AVSS+0.1V
Version 1.0
4
DEC 7 ,2001
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
