NT3960
TFT LCD Source Driver
Features
Output : 300/309 output channels
6-bit resolution /64 gray scale
Dot inversion with polarity control
V1 ~ V10 for adjusting Gamma correction
Power for analog circuit : 6.5 ~ 10V
Output dynamic range : 0.1 ~ AV
DD
-0.1V
Power consumption of analog circuit : 2.5mA
Power for interface circuit : 3.0 ~ 3.6V
Operating frequency : 65MHz
Output deviation : 10 ~ 20mV
Data inverting for reducing EMI
Cascade function with bi-direction shift control
CMOS silicon gate ( p-type substrate )
COG
General Description
NT3960 is a data driver IC for a color TFT LCD panel. The channel number of 300 or 309 outputs is selectable for
SVGA and XGA applications. For better performance, dot inversion and a wide range voltage output, 6.5~10V, are designed
in this chip and for reducing EMI, data inversion control is used. This chip also supplies 10 sections of voltage-reference for
Gamma correction.
Block Diagram
OUT1
OUT2
OUT3
OUT309
OUT308
Out Driver Buffer ( 309 channels )
V1 ~ V10
10
Digital to Analog Converter
6
6
6
6
6
POL
Level Shift
6
6
6
Decoder
6
6
6
6
6
6
6
6
D00 ~ D05
D10 ~ D15
D20 ~ D25
Line Latch ( 309 X 6 bits X 2 )
LD
REV
DIO1
1
103
Shift Registers ( 103 or 100 )
DIO2
Vcc
GND AVDD AVSS
CLK
SHL
SELT
1
V1.0
NT3960
TFT LCD Source Driver
Pin Configuration (IC face view)
PASS1
PASS2
PASS3
DIO2
AVDD
AVSS
GND
Vcc
REV
SHL
GND
POL
LD
D25
D24
D23
NC
D22
D21
D20
Test
SELT
AVSS
V10
V9
V8
V7
V6
V5
V4
V3
V2
V1
AVDD
D15
D14
D13
NC
D12
D11
D10
NC
D05
D04
D03
NC
D02
D01
D00
NC
CLK
Vcc
GND
AVSS
AVDD
DIO1
PASS4
PASS5
PASS6
PASS1
PASS2
PASS3
OUT309
OUT308
OUT307
OUT306
OUT305
NT3960
OUT5
OUT4
OUT3
OUT2
OUT1
PASS4
PASS5
PASS6
2
NT3960
TFT LCD Source Driver
Pad Description
Pad No.
Designation I/O
Description
Data input. For three 6-bit data,1 pixel, of color data (R, G, B)
I
DX5 : MSB; DX0 : LSB
132~140,142~150, D05 ~ D00
112~120,122~130, D15 ~ D10
47~55, 57~65
31 ~ 34
D25 ~ D20
REV
I
Controls whether data is inverted or not.
When “REV”=1 the data will be inverted. EX. “00”
and so on.
“ 3F”, “07”
“ 38”, “15”
“2A”,
152 ~ 155
69 ~ 71
CLK
SELT
I
I
Clock signal; latching data onto the line latches at the rising edge.
Selects the output channel number; when SELT= “0” : 309 channels; and “1” = 300
channels (OUT151~ OUT159 are in-available ). There is a 100K internal pull-up
resistor with this pin.
Gamma correction reference voltage. The voltage of these pins must be AVSS<
V10< V9< V8<V7<V6; V5<V4<V3<V2<V1< AVDD
106 ~ 77
189 ~ 497
V1 ~ V10
OUT1 ~
OUT309
SHL
I
O Output drive signals;
If 300-channel function is selected, OUT151~ OUT159 are in-available.
I
Selects left or right shift;
SHL=“1” : DIO1 OUT1,2,3 OUT4,5,6 OUT7,8,9--- OUT307,308,309= DIO2
SHL=“0” : DIO1=OUT1,2,3 OUT4,5,6 OUT7,8,9 --- OUT307,308,309 DIO2
SHL
1
0
DIO1
Input
Output
DIO2
Output
Input
SHIFT
Right
Left
35 ~ 37
176 ~ 178
8 ~ 10
DIO1
DIO2
I/O Start pulse signal input/output
When SHL is applied high (SHL="1"), a start high-pulse on DIO1 is latched at the
rising edge of the CLK. Then the data are latched serially onto internal latches at
the rising edge of the CLK. After all line latches are full with data, 100/103 clocks, a
pulse is shifted out through the DIO2 pin at the rising edge of the CLK. This function
can cascade two or more devices for dot expansion. In normal applications, the
DIO2 signal of the first device is connected to the DIO1 of the second stage, and the
DIO2 of the second one is connected to the DIO1 of the third, and so on like a daisy
chain.
In contrast, when SHL is applied low, a start pulse inputs on DIO2, and outputs
through DIO1.
*Remark : The input pulse-width of DIO1/2 may be over 1 clock-cycle.
44 ~ 46
LD
I
Latches the polarity of outputs and switches the new data to outputs.
1. At the rising edge, latches the “POL” signal to control the polarity of the outputs.
2. The pin also controls the switch of the line registers that switches the new
incoming data
to outputs.
*Remark : The LD may switch the new data to outputs at anytime even if the line
data are not completely full.
3
NT3960
TFT LCD Source Driver
Pad Description (continued)
Pad No.
41 ~ 43
Designation I/O
POL
I
Description
Polarity select for the dot-inversion control. Available at the rising edge of LD
“POL” value is latched at the rising edge of “LD” to control the polarity of the even or
odd outputs. “POL=1” represents that the next-line odd outputs are of positive
polarity with a voltage output range from V1~V5, and even outputs are of negative
polarity with a voltage output range from V6 to V10. On the other hand, if LD gets
low level “POL”, odd outputs are of negative polarity and even outputs are of
positive.
POL=1: Odd outputs range from V1 ~ V5
Even outputs range from V6 ~ V10
POL=0: Odd outputs range from V6 ~ V10
Even outputs range from V1 ~ V5
*Remark: Pay attention to the polarity when selecting the 300-channel function.
The polarity of OUT160 ~OUT309 must be changed. (The polarity needs to
be continuous, +, -, +, -, +, -, etc. If you don’t change the polarity, it will not be
continuous between OUT150 and OUT160 when selecting the 300-channel
function. )
11~15, 107~111,
171~175
16 ~ 20, 72 ~ 76,
166 ~ 170
26 ~ 30, 156 ~ 160
21 ~ 25, 38 ~ 40,
161 ~ 165
66 ~ 68
5~7, 500~498
179~181,188~186
501, 502
1~4, 182 ~ 185,
56, 121, 131, 141,
151
Test
PASS1~3
PASS4~6
Align Mark
NC
-
-
For COG assembly alignment
No connected
-
-
For testing
The internal connected paths
Vcc
GND
I
I
Power supply for digital circuits
Ground pins for digital circuits
AVSS
I
Ground pins for analog circuits
AVDD
I
Power supply for analog circuits ; 6.5 ~ 10V
4
NT3960
TFT LCD Source Driver
Power on/off sequence:
This IC is a high-voltage LCD driver, so may be damaged by a large current flow when an incorrect power sequence is used.
First connecting the logical power, Vcc & GND and then the drive power, AVDD&AVSS with V1~V10 as the last is the
recommended sequence. When shutting off the power, first shut off the drive power and then the logic system, or turn off all
power simultaneously.
Relationship between input data and output channels
(1) SHL=”1” , shift right, a start pulse from DIO1
Output
OUT1
OUT2
OUT3
Order
First data
Data
D05~D00 D15~D10 D25~D20
(2) SHL=”0”, shift left, a start pulse from DIO2
Output
OUT1
OUT2
OUT3
Order
Last data
Data
D05~D00 D15~D10 D25~D20
---
---
---
---
---
---
OUT307
D05~D00
OUT307
D05~D00
OUT308
Last data
D15~D10
OUT308
First data
D15~D10
OUT309
D25~D20
OUT309
D25~D20
Relationship between input data and output voltage
The figure below shows the relationship between the input data and the output voltage with the polarity. The range of
V1~V5 is for positive polarity, and V6 ~ V10 for negative polarity. Please refer to the following pages to get the relative resistor
value and voltage calculation method.
Gamma correction diagram
Vout
AVDD
V1
V2
V3
V4
V5
Vcom
V6
V7
V8
Negative polarity
V9
Positive polarity
V10
AVSS
00H
08H
10H
18H
20H
28H
30H
38H
3FH
Input Data
Remark : AV
DD
-0.1 > V1 > V2 > V3 > V4 > V5 ; V6 > V7 > V8 > V9 > V10 >AVSS+0.1V
Actual application( for reference only): AVD
D
=8.4V, V1=8.2V, V2=7.16V, V3=6.72V, V4=6.38V,
V5=4.98V, V6=3.44V, V7=2.08V, V8=1.70V, V9=1.28V, V10=0.20V.
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
