IEEE 488.2 Controller Chip
NAT9914
Pin compatible with TI TMS9914A
Software compatible with
NEC µPD7210 or TI TMS9914A
controller chips
Low power consumption
Meets all IEEE 488.2 requirements
Bus line monitoring
Preferred implementation of
requesting service
Will not send messages when there
are no Listeners
Performs all IEEE 488.1
interface functions
Programmable data transfer rate
(T1 delays of 350 ns, 500 ns,
1.1 µs, and 2 µs)
Automatic EOS and/or NL message
detection
Direct memory access (DMA)
Automatically processes IEEE 488
commands and reads
undefined commands
TTL-compatible CMOS device
Programmable clock rate
20 MHz maximum
Reduces driver overhead
Does not lose a data byte
if ATN is asserted while
transmitting data
ni.com/store
Description
The NAT9914 IEEE 488.2 controller chip can perform all the
interface functions defined by the IEEE Standard 488.1-1987, and
also meets the additional requirements and recommendations
of the IEEE Standard 488.2-1987. Connected between the
processor and the IEEE 488 bus, the NAT9914 provides high-
level management of the IEEE 488 bus, significantly increases
the throughput of driver software, and simplifies both the
hardware and software design. The NAT9914 performs
complete IEEE 488 Talker, Listener, and Controller functions. In
addition to its numerous improvements, the NAT9914 is also
completely pin compatible with the TI TMS 9914A and
software compatible with the NEC µPD7210 and TI TMS9914A
controller chips.
General
The NAT9914 manages the IEEE 488 bus. You program the
IEEE 488 bus by writing control words into the appropriate
registers. CPU-readable status registers supply operational
feedback. The NAT9914 mode determines the function of
these registers. On power up or reset, the NAT9914 registers
resemble those of the TMS9914A set, with additional registers that
supply extra functionality and IEEE 488.2 compatibility. In this
mode, the NAT9914 is completely pin compatible with
the TI TMS9914A. If you enable the 7210 mode, the registers
resemble those of the NEC µPD7210 set, with additional registers
that supply extra functionality and IEEE 488.2 compatibility. This
mode is not pin compatible with the NECµPD7210. Figure 4
shows the key components of the NAT9914.
IEEE 488.2 Overview
The IEEE 488.2 standard removes the ambiguities of IEEE 488.1
by standardizing the way instruments and controllers operate. It
defines data formats, status reporting, error handling, and
common configuration commands to which all IEEE 488.2
instruments must respond in a precise manner. It also defines a
set of controller requirements. With IEEE 488.2, you gain the
benefits of reduced development time and cost because systems
are more compatible and reliable. The NAT9914 brings the full
power of IEEE 488.2 to the design engineer along with
numerous other design and performance benefits, while
retaining the 40-pin and 44-pin hardware configurations of the
TI TMS 9914A.
IEEE 488.2 Controller Chip
ACCRQ
ACCGR
CE
WE
DBIN
RS0
RS1
RS2
INT
D7
D6
D5
D4
D3
D2
D1
D0
CLK
RESET
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
TR
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
DIO8
CONT
SRQ
ATN
EOI
DAV
NRFD
NDAC
IFC
REN
TE
Pin Identification
PLCC
11, 12, 13,
14, 15, 16,
17, 19
4
Pin Number
DIP
QFP
10, 11, 12, 16, 17, 18,
13, 14, 15,
16, 17
3
19, 20, 21,
22, 24
9
CE*
I
Mnemonic
D(7-0)
Type
I/O
†
NAT9914BPD
Description
Bidirectional 3-state data bus transfers
commands, data, and status between the
NAT9914 and the CPU.
D0 is the most significant bit.
Chip Enable gives access to the register
selected by a read or write operation, and the
register selects RS(2-0).
With the Data Bus Input, you can place the
contents of the register selected by RS(2-0)
and CE* onto the data bus D(7-0). The polarity
of DBIN is reversed for DMA operation.
The Write input latches the contents of the
data bus D(7-0) into the register selected by
RS(2-0).
The Access Grant signal selects the DIR or
CDOR for the current read or write cycle.
The Access Request output asserts to request
a DMA Acknowledge cycle.
The CLK input can be up to 20 MHz.
Asserting the RESET* input places the
NAT9914 in an initial, idle state.
The Interrupt output asserts when one of the
unmasked interrupt conditions is true. The
NAT9914 does not drive INT* high. The INT*
pin must be pulled up by an external resistor.
6
Figure 1. NAT9914BPD
Pin Configuration
5
DBIN
WE
CE
ACCGR
ACCRQ
NC
VDD
TR
DIO1
DIO2
NC
5
11
DBIN
I
†
4
10
WE*
I
RS0
RS1
RS2
INT
D7
D6
D5
D4
D3
D2
D1
6 5 4 3 2 1 44 43 42 41 40
7
39
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
18 19 20 21 22 23 24 25 26 27 28
NAT9914BPL
DIO3
DIO4
DIO5
DIO6
DIO7
DIO8
CONT
SRQ
ATN
EOI
DAV
3
2
20
21
10
2
1
18
19
9
8
7
25
26
15
ACCGR*
ACCRQ*
CLK
RESET*
INT*
(OC)
I
†
O
I
I
†
†
NC
D0
CLK
RESET
VSS
TE
REN
IFC
NDAC
NRFD
NC
O
Figure 2. NAT9914BPL
Pin Configuration
NC
NRFD
NDAC
IFC
REN
TE
V
SS
RESET
CLK
D0
NC
9, 8, 7
25
D1
D2
D3
D4
D5
D6
D7
INT
RS2
RS1
RS0
8, 7, 6
23
22
28
14, 13, 12
30
29
36
RS(2-0)
IFC*
REN*
ATN*
I
†††
DAV
EOI
ATN
SRQ
CONT
DIO8
DIO7
DIO6
DIO5
DIO4
DIO3
33 32 31 30 29 28 27 26 25 24 23
34
22
21
35
20
36
19
37
18
38
17
39
16
40
15
41
14
42
13
43
12
44
1 2 3 4 5 6 7 8 9 10 11
I/O
,
† ††
The Register Selects determine which register
to access during a read or write operation.
Bidirectional control line initializes the
IEEE 488 interface functions.
Bidirectional control line selects either remote
or local control of devices.
Bidirectional control line indicates whether
data on the DIO lines is an interface or device-
dependent message.
Bidirectional control line requests service from
the controller.
8-bit bidirectional IEEE 488 data bus
24
31
NAT9914BPQ
(OC)
I/O
(OC)
†
I/O
†
32
NC
DIO2
DIO1
TR
V
DD
NC
ACCRQ
ACCGR
CE
WE
DBIN
29
31, 32, 33,
34, 35, 36
37, 38
26
25
24
27
21
37
39, 40, 41,
42, 43, 44,
2, 3
34
32
31
35
28
SRQ*
DIO(8-1)*
I/O
†
34, 35, 36,
37, 38, 39,
41, 42
29
27
26
30
23
I/O
†
Figure 3. NAT9914BPQ
Pin Configuration
DAV*
NRFD*
NDAC*
EOI*
TE
I/O
†
Handshake line indicates that the data on the
DIO(8-1)* lines is valid.
Handshake line indicates that the device is
ready for data.
Handshake line indicates the completion of a
message reception.
Bidirectional control line indicates the last byte
of a data message or executes a parallel poll.
Talk Enable controls the direction of the
IEEE 488 data transceiver.
I/O
I/O
I/O
O
†
†
†
†
2
National Instruments
Tel: (512) 794-0100 • Fax: (512) 683-9300 • info@ni.com • ni.com/gpib
IEEE 488.2 Controller Chip
PLCC
43
33
44
22
1, 18,
28,40
OC= Open collector.
†
Pin Number
DIP
39
30
40
20
–
QFP
4
38
5
27
1, 6,
23, 33
Mnemonic
TR
CONT*
VDD
VSS
NC
Type
O
O
–
–
†
†
Description
Trigger asserts when one of the trigger conditions is satisfied.
Controller asserts when the NAT9914 is Controller-In-Charge.
Power pin – +5 V (±5%)
Ground pin – 0 V
No connect
–
The pin contains an internal pull-up resistor of 25 kΩ to 100 kΩ.
In controller applications where the CLK signal frequency is > 8 MHz, IFC* should be pulled up with a 4.7 kΩ resistor.
RS0 and RS1 contain an internal pull-up resistor of 25 kΩ to 100 kΩ. RS2 does not contain an internal pull-up or pull-down resistor.
* Active low.
††
†††
D(7-0)
CE*
RS(2-0)
DBIN
WE*
ACCRQ*
ACCGR*
Read/
Write
Control
Data-In
DIO(8-1)*
Command Pass Through
Message
Decoder
Command/Data Out
Interface
Functions
SH1
Address Mode
AH1
T5/TE5
L3/LE3
End-of-String
Compare
SR1
RL1
PP1/PP2
Interrupt Status 0, 1, 2
Compare
CONT*
TE
TR
Address Status
Address
Interrupt Mask 0, 1, 2
INT*
CLK
Internal Count
Internal Count 2
DC1
DT1
C1-C5
Serial Poll
RSV Gen
Parallel Poll
EOI Gen
Aux A, B, E, F, G, I
STB Out
SYNC
SASR
RESET*
Auxiliary
Command Decoder
Bus Status
and Control
Version
GPIB
Control
Figure 4. NAT9914 Block Diagram
National Instruments
Tel: (512) 794-0100 • Fax: (512) 683-9300 • info@ni.com • ni.com/gpib
3
IEEE 488.2 Controller Chip
9914 Mode Registers
In 9914 mode, the NAT9914 registers consist of all the
TI TMS9914A registers and two types of additional registers – newly
defined registers and paged-in registers. The NAT9914 maps the newly
defined registers into the unused portion of the 9914 address space.
Each paged-in register appears at Offset 2 immediately after you issue an
auxiliary page-in command, and it remains there until you page another
register into the same space or you issue a reset. The table below lists all
the registers in the 9914 register set. See the NAT9914 Reference Manual
available at
ni.com
for more information.
7210 Mode Registers
The NAT9914 registers include all the NEC µPD7210 registers plus two
types of additional registers – extra auxiliary registers and paged-in
registers. You write the extra auxiliary registers the same as standard
µPD7210 auxiliary registers. On issuing an auxiliary page-in command,
the paged-in registers appear at the same offsets as existing µPD7210
registers. At the end of the next CPU access, the chip pages out the
paged-in registers. The following table lists all the registers in the 7210
mode register set. See the NAT9914 Reference Manual available at
ni.com
for more information.
9914 Register Set
Register
Interrupt Status 0
Interrupt Mask 0
Interrupt Status 1
Interrupt Mask 1
Address Status
Interrupt Mask 2
End-of-String
Bus Control
Accessory
†
†
7210 Register Set
PAGE-IN
U
U
U
U
U
P
P
P
P
U
U
P
U
P
U
U
U
U
U
U
U
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
X
1
X
RS(2-0)
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
X
1
X
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
X
1
X
WE*
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
1
X
0
0
DBIN
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
CE* ACCGR*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
Register
Data-In
Data-In
Command/Data Out
Command/Data Out
Interrupt Status 1
Interrupt Mask 1
Interrupt Status 2
Interrupt Mask 2
Serial Poll Status
Serial Poll Mode
Version
Internal Counter 2
Address Status
Address Mode
Command Pass Through
Auxiliary Mode
Source/Acceptor Status
Address 0
Address
Interrupt Status 0
Interrupt Mask 0
Address 1
End-of-String
Bus Status
†
†
†
†
PAGE-IN
U
X
U
X
U
U
U
U
N
N
P
P
U
U
N
U
P
N
N
P
P
N
N
P
†
A(2-0)
0
X
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
X
0
X
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
X
0
X
1
1
0
0
1
1
1
1
0
0
1
1
1
0
0
0
0
1
1
1
1
WE*
1
X
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
DBIN
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
CE*
0
X
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ACCGR*
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
†
†
Bus Status
Auxiliary Command
Interrupt Status 2
Address
Serial Poll Status
Serial Poll Mode
Command Pass Through
Parallel Poll
Data-In
Data-In
Command/Data Out
Command/Data Out
†
†
†
The ' ' symbol denotes features (such as registers and auxiliary commands) that are not available in the TMS9914A.
Notes for the PAGE-IN column:
U = Page-in auxiliary commands do not affect
the register offset.
P = The register offset is valid only after a page-in
auxiliary command.
Bus Control
†
P
The ' ' symbol denotes features (such as registers and auxiliary commands) that are not available in the NEC7210.
Notes for the PAGE-IN column:
U = The page-in auxiliary command does not affect
the register.
N = The register offset is always valid except for immediately
after a page-in auxiliary command.
P = The register is valid only immediately after a page-in
auxiliary command.
4
National Instruments
Tel: (512) 794-0100 • Fax: (512) 683-9300 • info@ni.com • ni.com/gpib
IEEE 488.2 Controller Chip
Preliminary DC Characteristics
T
A
0 to 70 °C; V
CC
= 5 V ±5%
Limits
Parameter
Voltage input low
Voltage input high
Voltage output low
Voltage output high
Input/output
Leakage current
Input/output
Leakage current
Supply current
Output current low
All pins except ACCRQ
ACCRQ
Input current low
Supply voltage
Symbol
V
IL
V
IH
V
OL
V
OH
–
–
–
I
OL
I
OL
I
IL
V
DD
Min
-0.5
+2.0
0
+2.4
-10
-200
–
2
4
–
4.75
Max
+0.8
V
CC
0.4
VCC
+10
+200
45
–
–
- 0.5
5.25
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
V
Test
Condition
–
–
–
–
without
internal pull-up
with internal
pull-up
–
0.4 V @ I
OL
0.4 V @ I
OL
–
–
Absolute Maximum Ratings
Property
Supply voltage, V
DD
Input voltage, V
I
Operating temperature, T
OPR
Storage temperature, T
STG
Range
-0.5 to +7.0 V
-0.5 to V
DD
+0.5 V
0 to +70° C
-40 to +125° C
Comment: Exposing the device to stresses above those listed could cause permanent damage. The
device is not meant to be operated under conditions outside the limits described in the operational
section. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
AC Characteristics
T
A
0 to 70 °C; V
CC
= 5 V ±5%
Limits
Parameter
Address hold from CE, WE,and DBIN
Address setup to CE , WE, and DBIN
Data float from CE or DBIN
Data delay from DBIN↓
ACCRQ unassertion
Data delay from CE↓
CE recovery width
CE pulse width
Data hold from WE↑
Data setup to WE↑
Symbol
t
AH
t
AS
t
DF
t
DR
t
DU
t
RD
t
RR
t
RW
t
WH
t
WS
Min
0
0
–
–
–
–
80
80
0
60
Max
–
–
20
75
20
80
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Condition
–
–
–
ACCGR=0
–
ACCGR=1
–
–
–
–
Capacitance
T
A
0 to 70 °C; V
CC
= 5 V ±5%
Parameter
Input
capacitance
Output
capacitance
I/O capacitance
Symbol
C
IN
C
OUT
C
I/O
Limits
Min
Max
–
10
–
–
10
10
Unit
pF
pF
pF
Test
Condition
–
–
–
Notes:
•
t
AS
is the setup time to CE↓ or WE↓ , whichever is later.
•
t
AH
is the hold time from WE↑ or CE↑ , whichever is earlier.
Timing Waveforms
t
AS
t
AH
RS2-0
DBIN
RS2-RS0
t
AS
t
AH
CE
t
RD
t
DF
CE
D7-0
t
RW
t
RR
WE
t
WS
t
WH
D7-0
Figure 5. CPU Read
Figure 7. CPU Write
t
DU
ACCRQ
ACCGR
DBIN
D7-0
t
DR
ACCRQ
t
DU
ACCGR
DBIN
t
DF
WE
t
WS
t
WH
D7-0
Figure 6. DMA Read
Figure 8. DMA Write
National Instruments
Tel: (512) 794-0100 • Fax: (512) 683-9300 • info@ni.com • ni.com/gpib
5
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