RDRAM
512Mb (1024Kx16/18x32s)
Advance Information
Overview
The RDRAM device is a general purpose high-performance
memory device suitable for use in a broad range of applications
including computer memory, graphics, video, and any other
application where high bandwidth and low latency are required.
The 512/576 Mb RDRAM devices are extremely high-speed
CMOS DRAMs organized as 32M words by 16 or 18 bits. The
use of Rambus Signaling Level (RSL) technology permits
800MHz to 1600MHz transfer rates while using conventional
system and board design technologies. RDRAM devices are
capable of sustained data transfers up to 0.625ns per two bytes
(5.0 ns per sixteen bytes).
The architecture of the RDRAM devices allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and data
buses with independent row and column control yield over
95% bus efficiency. The RDRAM device’s 32 banks support
up to four simultaneous transactions.
System-oriented features for mobile, graphics and large mem-
ory systems include power management, byte masking, and
x18 organization. The two data bits in the x18 organization are
general and can be used for additional storage and bandwidth
or for error correction.
Figure 1: 1600 MHz RDRAM CSP Package
The 512/576 Mb RDRAM devices are offered in a CSP hori-
zontal package suitable for desktop as well as low-profile add-
in card and mobile applications.
Key Timing Parameters/Part Numbers
Organization
a
1024Kx16x32s
1024Kx16x32s
1024Kx16x32s
1024Kx16x32s
1024Kx16x32s
1024Kx16x32s
1024Kx16x32s
1024Kx16x32s
1024Kx16x32s
1024Kx16x32s
1024Kx16x32s
1024Kx16x32s
1024Kx18x32s
1024Kx18x32s
1024Kx18x32s
1024Kx18x32s
1024Kx18x32s
1024Kx18x32s
1024Kx18x32s
1024Kx18x32s
1024Kx18x32s
1024Kx18x32s
1024Kx18x32s
1024Kx18x32s
I/O Freq.
MHz
800
800
1066
1066
1066
1066
1200
1200
1333
1333
1600
1600
800
800
1066
1066
1066
1066
1200
1200
1333
1333
1600
1600
Timing Bin
45
40
35
32
32P
30
32
30
31
28
31
27
45
40
35
32
32P
30
32
30
31
28
31
27
Part
Number
512Ms-45-800
512Ms-40-800
512Ms-35-1066
512Ms-32-1066
512Ms-32P-1066
512Ms-30-1066
512Ms-32-1200
512Ms-30-1200
512Ms-31-1333
512Ms-28-1333
512Ms-31-1600
512Ms-27-1600
576Ms-45-800
576Ms-40-800
576Ms-35-1066
576Ms-32-1066
576Ms-32-1066
576Ms-30-1066
576Ms-32-1200
576Ms-30-1200
576Ms-31-1333
576Ms-28-1333
576Ms-31-1600
576Ms-27-1600
Features
•
High sustained bandwidth per DRAM device
•Up to 3.2 GB/s sustained data transfer rate
•Separate control and data buses for maximized efficiency
•Separate row and column control buses for easy schedul-
ing and highest performance
•32 banks: four transactions can take place simultaneously
at full bandwidth data rates
Low latency features
•Write buffer to reduce read latency
•3 precharge mechanisms for controller flexibility
•Interleaved transactions
Advanced power management:
•Multiple low power states allows flexibility in power
consumption versus time to transition to active state
•Power-down self-refresh
Organization: 2 KB pages and 32 banks, x 16/18
•x18 organization allows ECC configurations or increased
storage/bandwidth
•x16 organization for low cost applications
Uses RSL for up to 1600MHz operation
•
•
a. The bank designations are described in "Row and Column Cycle
Description" on page 17.
32s - 32 banks that use a “split” bank architecture.
Related Documentation
Datasheets for the RDRAM memory system components are
available on the Rambus website at
www.rambus.com.
Please
obtain the "Documentation Change History"for this datasheet.
The DCH is an integral part of the data sheet and contains the
most recent information about changes made to the published
version. Check the RDRAM website regularly for the latest
DCH and datasheet updates.
Version 0.3
•
•
DL-0205-01
Advance Information
Rambus Confidential
512Mbit RDRAM
Pinouts and Definitions
Center-Bonded Devices - Preliminary
This table shows the pin assignments of the center-bonded
RDRAM package. The mechanical dimensions of this package
are shown in a later section. "Center-Bonded uBGA Package
(16x6)" on page 63.
Table 1
Center
Bonded Device (top view)
10
9
8
7
6
5
4
3
2
1
A
VDD
GND
VDD
GND VDD
VDD
VDD
VDD
GND VDD
GND VDD
VDD
CMD
VDD
GND GNDa GNDa VDD
CTM
VDD
GND GND VDD
VDD
GND GND VCMO VDD
S
GND
DQA8 DQA7 DQA5 DQA3 DQA1 CTM
ROW2 ROW0 COL3 COL1 DQB1 DQB3 DQB5 DQB7 DQB8 VDD
GND GND DQA6 DQA4 DQA2 DQA0 CFM
VDD
GND SCK
VCMO GND VDD
S
CFM
ROW1 COL4 COL2 COL0 DQB0 DQB2 DQB4 DQB6 GND GND
GND GND VDD
SIO0
SIO1
GND VDD
GND VDDa VREF GND VDD
VDD
B
GND
C
D
GND VDD
E
F
GND
G
H
J
K
L
GND GND GND
M
N
P
R
GND VDD
S
T
U
Note the following:
• This is the “Top View” (balls facing down, backside of
chip facing up).
•
•
Pin #1 designation is at location A1.
Columns “A” and “U”, and Rows “1” and “10” can be
deleted when die size shrink to the point that those balls
will not fall within the die boundaries.
For x16 devices either DQA8 & DQB8 must be defined
as no connects or columns “B” and “T” must be deleted
completely.
•
2
Advance Information
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512Mbit RDRAM
Table 2
Pin
Signal
SIO1,SIO0
CMD
SCK
V
DD
V
DDa
V
CMOS
GND
GNDa
DQA8..DQA0
I/O
RSL
b
I/O
I/O
I
I
Type
CMOS
a
CMOS
a
CMOS
a
# Pins
edge
2
1
1
14
2
2
19
2
9
# Pins
center
2
1
1
6
1
2
9
1
9
Description
Description
Serial input/output. Pins for reading from and writing to the control registers using a
serial access protocol. Also used for power management.
Command input. Pins used in conjunction with SIO0 and SIO1 for reading from and
writing to the control registers. Also used for power management.
Serial clock input. Clock source used for reading from and writing to the control regis-
ters
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Nine pins which carry a byte of read or write data between the Channel
and the RDRAM device. DQA8 is not used by RDRAM devices with a x16 organiza-
tion.
Clock from master. Interface clock used for receiving RSL signals from the Channel.
Positive polarity.
Clock from master. Interface clock used for receiving RSL signals from the Channel.
Negative polarity
Logic threshold reference voltage for RSL signals
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
Clock to master. Interface clock used for transmitting RSL signals to the Channel. Pos-
itive polarity.
Row access control. Three pins containing control and address information for row
accesses.
Column access control. Five pins containing control and address information for col-
umn accesses.
Data byte B. Nine pins which carry a byte of read or write data between the Channel
and the RDRAM device. DQB8 is not used by RDRAM devices with a x16 organiza-
tion.
CFM
CFMN
V
REF
CTMN
CTM
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB8..DQB0
I
I
RSL
b
RSL
b
1
1
1
1
1
1
1
1
3
5
9
I
I
I
I
I/O
RSL
b
RSL
b
RSL
b
RSL
b
RSL
b
1
1
3
5
9
Total pin count per package
74
54
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
DL-0205-01
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512Mbit RDRAM
RQ7..RQ5 or
ROW2..ROW0
3
RQ4..RQ0 or
COL4..COL0
5
DQB8..DQB0
9
CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN
2
2
RCLK
DQA8..DQA0
9
RCLK
1:8 Demux
TCLK
Packet Decode
ROWR
ROWA
11
5
5
BR
10
R
REFR Power Modes DEVID
ROP DR
AV
1:8 Demux
RCLK
Control Registers
6
XOP
M
COLX
5
5
DX
Packet Decode
COLC
5
5
5
BC
7
C
8
BX COP DC
S
COLM
8
MA
MB
Match
DM
Mux
Row Decode
Match
XOP Decode
Match
Write
Buffe
Mux
r
Mux
PRER
ACT
Sense Amp
64x72
SAmp SAmp SAmp
PREX
Column Decode & Mask
DRAM Core
64x72 1024x128x144
0
64x72
72
SAmp SAmp SAmp
0
0/1
1/2
PREC
RD, WR
Internal DQB Data Path
72
Internal DQA Data Path
Bank 0
0/1
72
Bank 1
1/2
72
RCLK
9
9
•••
Bank 2
9
•••
9
RCLK
SAmp SA
mp
SAmp
15
14
/15 13/14
Bank 13
Bank 14
Bank 15
•••
13/14 14/15
SAmp SAmp SAmp
Write Buffer
Write Buffer
1:8 Demux
9
1:8 Demux
9
15
SAmp SAmp SAmp
SAmp SAmp SAmp
16
16
17/18 16/17
Bank 16
Bank 17
Bank 18
16/17 17/18
TCLK
9
9
TCLK
•••
•••
•••
8:1 Mux
9
8:1 Mux
9
30/31 29/30
SAmp SAmp SAmp
Bank 29
Bank 30
Bank 31
29/30 30/31
31
SAmp SAmp SAmp
Figure 2: 512/576 Mb ((1024Kx16/18x32s)) RDRAM Device Block Diagram
4
31
Advance Information
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Version 0.3
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512Mbit RDRAM
COL Pins:
The principle use of these five pins is to manage
the transfer of data between the DQA/DQB pins and the
sense amps of the RDRAM device. These pins are de-multi-
plexed into a 23-bit COLC (column-operation) packet and
either a 17-bit COLM (mask) packet or a 17-bit COLX
(extended-operation) packet.
General Description
Figure 2 is a block diagram of the 512/576 Mb RDRAM
device. It consists of two major blocks: a core block built from
banks and sense amps similar to those found in other types of
DRAM, and a Direct Rambus interface block which permits an
external controller to access this core at up to 3.2GB/s.
Control Registers:
The CMD, SCK, SIO0, and SIO1 pins
appear in the upper center of Figure 2. They are used to write
and read a block of control registers. These registers supply the
RDRAM device configuration information to a controller and
they select the operating modes of the device. The REFR value
is used for tracking the last refreshed row. Most importantly,
the five bit DEVID specifies the device address of the
RDRAM device on the Channel.
ACT Command:
An ACT (activate) command from an
ROWA packet causes one of the 1024 rows of the selected
bank to be loaded to its associated sense amps (two 512 bytes
sense amps for DQA and two for DQB).
PRER Command:
A PRER (precharge) command from
an ROWR packet causes the selected bank to release its two
associated sense amps, permitting a different row in that bank
to be activated, or permitting adjacent banks to be activated.
Clocking:
The CTM and CTMN pins (Clock-To-Master)
generate TCLK (Transmit Clock), the internal clock used to
transmit read data. The CFM and CFMN pins (Clock-From-
Master) generate RCLK (Receive Clock), the internal clock sig-
nal used to receive write data and to receive the ROW and
COL pins.
RD Command:
The RD (read) command causes one of
the 128 dualocts of one of the sense amps to be transmitted on
the DQA/DQB pins of the Channel.
WR Command:
The WR (write) command causes a dua-
loct received from the DQA/DQB data pins of the Channel to
be loaded into the write buffer. There is also space in the write
buffer for the BC bank address and C column address infor-
mation. The data in the write buffer is automatically retired
(written with optional bytemask) to one of the 128 dualocts of
one of the sense amps during a subsequent COP command. A
retire can take place during a RD, WR, or NOCOP to another
device, or during a WR or NOCOP to the same device. The
write buffer will not retire during a RD to the same device. The
write buffer reduces the delay needed for the internal DQA/
DQB data path turn-around.
DQA,DQB Pins:
These 18 pins carry read (Q) and write
(D) data across the Channel. They are multiplexed/de-multi-
plexed from/to two 72-bit data paths (running at one-eighth
the data frequency) inside the RDRAM device.
Banks:
The 32Mbyte core of the RDRAM device is divided
into 32 2.0 Mbyte banks, each organized as 1024 rows, with
each row containing 128 dualocts, and each dualoct containing
16 bytes. A dualoct is the smallest unit of data that can be
addressed.
Sense Amps:
The RDRAM device contains 34 sense amps.
Each sense amp consists of 1Kbyte of fast storage (512 bytes
for DQA and 512 bytes for DQB) and can hold one-half of
one row of one bank of the RDRAM device. The sense amp
may hold any of the 1024 half-rows of an associated bank.
However, each sense amp is shared between two adjacent
banks of the RDRAM device (except for sense amps 0, 15, 16,
and 31). This introduces the restriction that adjacent banks
may not be simultaneously accessed.
PREC Precharge:
The PREC, RDA and WRA com-
mands are similar to NOCOP, RD and WR, except that a pre-
charge operation is performed at the end of the column
operation. These commands provide a second mechanism for
performing precharge.
PREX Precharge:
After a RD command, or after a WR
command with no byte masking (M=0), a COLX packet may
be used to specify an extended operation (XOP). The most
important XOP command is PREX. This command provides a
third mechanism for performing precharge.
RQ Pins:
These pins carry control and address information.
They are broken into two groups. RQ7..RQ5 are also called
ROW2..ROW0, and are used primarily for controlling row
accesses. RQ4..RQ0 are also called COL4..COL0, and are used
primarily for controlling column accesses.
Packet Format
Figure 3 shows the formats of the ROWA and ROWR packets
on the ROW pins. Table 3 describes the fields which comprise
these packets. DR4T and DR4F bits are encoded to contain
both the DR4 device address bit and a framing bit which
allows the ROWA or ROWR packet to be recognized by the
RDRAM device.
The AV (ROWA/ROWR packet selection) bit distinguishes
ROW Pins:
The principle use of these three pins is to man-
age the transfer of data between the banks and the sense amps
of the RDRAM device. These pins are de-multiplexed into a
24-bit ROWA (row-activate) or ROWR (row-operation) packet.
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