Datasheet> 器件分类 > 存储> IDT70V7519S166DRI

文档预览

IDT70V7519S166DRI: 产品描述256K X 36 DUAL-PORT SRAM, 15 ns, PBGA256; 产品类别存储; 文件大小292KB，共22页; 制造商IDT(艾迪悌); 官网地址http://www.idt.com/

下载文档详细参数全文预览

IDT70V7519S166DRI概述

256K X 36 DUAL-PORT SRAM, 15 ns, PBGA256

IDT70V7519S166DRI规格参数

参数名称	属性值
功能数量	1
端子数量	256
最大工作温度	85 Cel
最小工作温度	-40 Cel
最大供电/工作电压	3.45 V
最小供电/工作电压	3.15 V
额定供电电压	3.3 V
最大存取时间	15 ns
加工封装描述	BGA-256
状态	ACTIVE
包装形状	SQUARE
包装尺寸	GRID 阵列, 低 PROFILE
表面贴装	Yes
端子形式	BALL
端子间距	1 mm
端子涂层	锡铅
端子位置	BOTTOM
包装材料	塑料/环氧树脂
温度等级	INDUSTRIAL
内存宽度	36
组织	256K × 36
存储密度	9.44E6 deg
操作模式	同步
位数	262144 words
位数	256K
内存IC类型	双端口静态随机存储器
串行并行	并行

文档预览

下载PDF文档

全文
预览

HIGH-SPEED 3.3V 256K x 36

SYNCHRONOUS

BANK-SWITCHABLE

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

IDT70V7519S

256K x 36 Synchronous Bank-Switchable Dual-ported

SRAM Architecture

–

64 independent 4K x 36 banks

– 9 megabits of memory on chip

Bank access controlled via bank address pins

High-speed data access

– Commercial: 3.4ns(200MHz)/3.6ns (166MHz)/4.2ns

(133MHz) (max.)

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1

Functional Block Diagram

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

CONTROL

LOGIC

MUX

4Kx36

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

0L-35L

I/O

CONTROL

MUX

4Kx36

MEMORY

ARRAY

(BANK 1)

MUX

I/O

CONTROL

I/O

0R-35R

11L

ADDRESS

DECODE

ADDRESS

DECODE

11R

BANK

DECODE

MUX

4Kx36

MEMORY

ARRAY

(BANK 63)

BANK

DECODE

NOTE:

1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.

As a result, it has unique operating characteristics.

Please refer to the functional description on page 19

for details.

MUX

TDI

TDO

JTAG

TMS

TCK

TRST

5618 drw 01

DECEMBER 2002

DSC 5618/5

推荐资源

器件捷径: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

热门器件

开源项目推荐更多

热门活动更多

热门文章更多

技术资料推荐更多