MIC59P60
Micrel
MIC59P60
8-Bit Serial-Input Protected Latched Driver
General Description
The MIC59P60 serial-input latched driver is a high-voltage
(80V), high-current (500mA) integrated circuit comprised of
eight CMOS data latches, a bipolar Darlington transistor
driver for each latch, and CMOS control circuitry for the
common CLEAR, STROBE, CLOCK, SERIAL DATA INPUT,
and OUTPUT ENABLE functions. Similar to the MIC5842,
additional protection circuitry supplied on this device includes
thermal shutdown, under voltage lockout (UVLO), and over-
current shutdown.
The bipolar/CMOS combination provides an extremely low-
power latch with maximum interface flexibility. The MIC59P60
has open-collector outputs capable of sinking 500mA and
integral diodes for inductive load transient suppression with
a minimum output breakdown voltage rating of 80V (50V
sustaining). The drivers can be operated with a split supply,
where the negative supply is down to –20V and may be
paralleled for higher load current capability.
Using a 5V logic supply, the MIC59P60 will typically operate
at better than 5MHz. With a 12V logic supply, significantly
higher speeds are obtained. The CMOS inputs are compat-
ible with standard CMOS, PMOS, and NMOS circuits. TTL
circuits may require pull-up resistors. By using the serial data
output, drivers may be cascaded for interface applications
requiring additional drive lines.
Each of these eight outputs has an independent over current
shutdown of 500 mA. Upon over-current shutdown, the
affected channel will turn OFF and the flag will go low until V
DD
is cycled or the ENABLE/RESET pin is pulsed high. Current
pulses less than 2µs will not activate current shutdown.
Temperatures above 165°C will shut down the device and
activate the error flag. The UVLO circuit prevents operation
at low V
DD
; hysteresis of 0.5V is provided.
Features
•
•
•
•
•
•
•
•
•
•
•
3.3 MHz Minimum Data-Input Rate
Output Current Shutdown (500mA Typical)
Under Voltage Lockout
Thermal Shutdown
Output Fault Flag
CMOS, PMOS, NMOS, and TTL Compatible
Internal Pull-Up/Pull-Down Resistors
Low Power CMOS Logic and Latches
High Voltage Current Sink Outputs
Output Transient-Protection Diodes
Single or Split Supply Operation
Ordering Information
Part Number
MIC59P60BN
MIC59P60BV
MIC59P60BWM
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
20-Pin Plastic DIP
20-Pin PLCC
20-Pin Wide SOIC
Functional Diagram
Pin Configuration
(DIP and SOIC)
CLEAR
1
2
SUB
THERMAL
SHUTDOWN
I LIMIT
20 FLAG
19 OUTPUT 1
18 OUTPUT 2
CLOCK
SERIAL
DATA IN
3
8-BIT SERIAL–PARALLEL SHIFT REGISTER
20 FLAG
7
SERIAL DATA OUT
VDD
VEE
CLOCK
SERIAL DATA IN
VSS
VDD
4
6
3
SHIFT REGISTER
VSS
5
LATCHES
8
9
MOS
BIPOLAR
STROBE
OUTPUT
ENABLE/RESET
4
5
6
7
8
9
17 OUTPUT 3
LATCHES
CLEAR
1
16 OUTPUT 4
15 OUTPUT 5
14 OUTPUT 6
13 OUTPUT 7
12 OUTPUT 8
11 K
UVLO
SERIAL DATA OUT
STROBE
THERMAL
SHUTDOWN
ILIMIT
11
K
19
18
17
16
15
14
13
12
SUB
2
VEE
10
OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8
OUTPUT
ENABLE/RESET
VEE 10
SUB
UVLO
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
August 2001
1
MIC59P60
MIC59P60
CLOCK
CLEAR
OUT 1
FLAG
VEE
Micrel
PLCC Pin
Configuration
Absolute Maximum Ratings
V
SS
= 0; T
A
= 25°C
Output Voltage (V
CE
) .................................................... 80V
Output Voltage (V
CE(SUS)
) ............................... 50V,
Note 1
V
DD
with Reference to V
SS
........................................... 15V
V
DD
with Reference to V
EE
........................................... 25V
Emitter Supply Voltage (V
EE
) ...................................... –20V
Input Voltage (V
IN
) ............................... –0.3V to V
DD
+0.3V
Protected Current ............................................ 1.5A,
Note 2
Power Dissipation (P
D
)
Plastic DIP (N) ......................................................... 2.0W
Derate above T
A
= +25°C ............................ 20mW/°C
PLCC (V) .................................................................1.4W
Derate above T
A
= +25°C ............................ 14mW/°C
Wide SOIC (WM) .................................................... 1.2W
Derate above T
A
= +25°C ............................ 12mW/°C
Operating Temperature (T
A
)
Plastic DIP (N), PLCC (V), SOIC (WM) .. –40°C to +85°C
Storage Temperature (T
S
) ....................... –65°C to +150°C
Junction Temperature (T
J
) ...................................... +150°C
ESD .........................................................................
Note 3
Note 1:
Note 2:
Note 3:
V SS
3
2
1
20
19
18
17
SERIAL DATA IN
VSS
VDD
SERIAL DATA OUT
STROBE
4
5
6
7
8
9
10
11
12
13
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
MIC59P60BV
16
15
14
OE/RESET
K
OUT 8
Typical Inputs
CLOCK
SERIAL
DATA IN
V DD
OUT 7
VEE
V DD
STROBE
OUTPUT
ENABLE
For inductive load applications.
Each channel. V
EE
connection must be designed to minimize
inductance and resistance.
Devices are input-static protected but can be damaged by
extremetly high static charges.
V SS
Typical Output Driver
K
OUT
N
3K
V
EE
Pin Description
Pin
1
2,10
3
4
5
6
7
8
9
Name
CLEAR
V
EE
CLOCK
SUB
Description
Sets All Latches OFF (open).
Output Ground (Substrate). Most negative voltage in the system connects
here.
Serial Data Clock. A CLEAR must also be clocked into the latches.
Serial Data Input pin.
Logic reference (Ground) pin.
Logic Positive Supply voltage.
Serial Data Output pin. (Flow through).
Output Strobe pin. Loads output latches when High. A STROBE is needed
to CLEAR latches.
When Low, Outputs are active. When High, device is inactive and reset
from a fault condition. An under voltage condition emulates a high OE/
RESET input.
Transient suppression diode's cathode common pin.
Open Collector outputs 8 through 1.
Error Flag. Open-collector output is Low upon Overcurrent Fault or
Overtemperature fault. OUTPUT ENABLE/RESET must be pulled high to
reset the flag and fault condition.
SERIAL DATA IN
V
SS
V
DD
SERIAL DATA OUT
STROBE
OUTPUT ENABLE/RESET
11
12—19
20
K
OUTPUT N
FLAG
MIC59P60
2
August 2001
MIC59P60
Micrel
Electrical Characteristics
V
DD
= 5V, V
SS
= V
EE
= 0V; T
A
= +25°C; unless noted.
Limits
Characteristic
Output Leakage Current
Collector-Emitter
Saturation Voltage
Collector-Emitter
Sustaining Voltage
Input Voltage
Symbol
I
CEX
V
CE(SAT)
Test Conditions
V
OUT
= 80V
V
OUT
= 80V, T
A
= +70°C
I
OUT
= 100mA
I
OUT
= 200mA
I
OUT
= 350mA
I
OUT
= 350mA, L = 2mH
50
1.0
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V,
Note 4
V
DD
= 12V
V
DD
= 10V
V
DD
= 5.0V
V
OL
= 0.4V
V
OH
= 12.0V
All Drivers ON, V
DD
= 12V
All Drivers ON, V
DD
= 10V
All Drivers ON, V
DD
= 5.0V
10.5
8.5
3.5
50
50
50
200
300
600
15
50
6.4
6.0
4.6
3.1
2.9
2.3
2.6
2.4
1.9
10.0
9.0
7.5
4.5
4.5
3.6
4.2
3.6
3.0
50
1.7
500
Note 5
3.5
3.0
4.0
3.5
165
10
4.5
4.0
2.0
Min.
Typ.
100
0.9
1.1
1.3
1.1
1.3
1.6
V
Max.
50
Unit
µA
V
CE(SUS)
V
IN(0)
V
IN(1)
V
V
V
Input Resistance
R
IN
kΩ
Flag Output Current
Flag Output Leakage
Supply Current
I
OL
I
OH
I
DD(ON)
mA
nA
mA
I
DD (1 OUTPUT)
One Driver ON, All others OFF, V
DD
= 12V
One Driver ON, All others OFF, V
DD
= 10V
One Driver ON, All others OFF, V
DD
= 5V
I
DD(OFF)
All Drivers OFF, V
DD
= 12V
All Drivers OFF, V
DD
= 10V
All Drivers OFF, V
DD
= 5.0V
V
R
= 80V
I
F
= 350mA
mA
mA
Clamp Diode
Leakage Current
Clamp Diode
Forward Voltage
Over Current
Shutdown Threshold
Start Up Voltage
Minimum Supply (V
DD
)
Thermal Shutdown
Thermal Shutdown Hysteresis
I
R
V
F
I
LIM
V
SU
V
DD MIN
µA
V
mA
V
V
°C
°C
Note 4:
Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure a minimum logic "1".
Note 5:
Undervoltage lockout is guaranteed to release device at no more than 4.5V, and disable the device at no less than 3.0V
August 2001
3
MIC59P60
MIC59P60
CLOCK
A
B
DATA IN
E
STROBE
C
F
D
Micrel
OUTPUT
ENABLE
G
OUT N
Timing Conditions
(T
A
= +25°C, Logic Levels are V
DD
and V
SS,
V
DD
= 5V)
A.
B.
C.
D.
E.
F.
G.
Typical Data Active Time Before Clock Pulse (Data Set-Up Time) ........................................................................... 75 ns
Minimum Data Active Time After Clock Pulse (Data Hold Time) .............................................................................. 75 ns
Minimum Data Pulse Width ..................................................................................................................................... 150 ns
Minimum Clock Pulse Width .................................................................................................................................... 150 ns
Minimum Time Between Clock Activation and Strobe ............................................................................................. 300 ns
Minimum Strobe Pulse Width ................................................................................................................................... 100 ns
Typical Time Between Strobe Activation and Output Transition ............................................................................. 500 ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL
DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Holding CLEAR high results in a data
logic "0" being clocked into the shift register, turning off respective channels.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion).
The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed
(STROBE tied high) will require that the ENABLE input be high to prevent invalid output states.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the latches
or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. A positive OE/RESET pulse
resets the FLAG and the output after a current shutdown fault. Over-temperature faults are not latched and require no reset
pulse.
MIC59P60 Truth Table
Serial
Data
Input
H
L
X
H
Shift Register Contents
Clear Clock
Input Input
I
1
H
L
R1
O
X
P
1
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
O = Output OFF
I
2
R
1
R
1
R2
O
X
P
2
I
3
……
R
2
……
R
2
……
R
3
……
O ……
X ……
P
3
……
I
8
R
7
R
7
R
8
O
X
P
8
Serial
Data
Output
R
7
R
7
R
8
L
X
P
8
Latch Contents
Strobe
Input
I
1
I
2
I
3
……
Output Contents
Output
I
8
Enable I
1
I
2
I
3
…… I
8
L
H
R
1
R
2
P
1
P
2
X
X
R
3
P
3
X
……
……
……
R
8
P
8
X
L
H
P
1
H
P
2
H
P
3
……P
8
H …… H
MIC59P60
4
August 2001
MIC59P60
Micrel
Typical Characteristic Curves
Output Saturation
Voltage vs. Temperature
SUPPLY CURRENT (mA)
1.5
SATURATION VOLTAGE (V)
5
4
3
2
1
0
–50
Supply Current
vs. Temperature
ALL OUTPUTS ON
V
DD
= 5V
SHUTDOWN THRESHOLD (A)
Current Shutdown
Threshold vs. Temperature
0.60
0.55
V
DD
= 5V
0.50
0.45
0.40
0.35
–50
V
DD
= 12V
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
–50
I
L
= 100mA
V
DD
= 5V to 12V
I
L
= 350mA
ALL OUTPUTS OFF
0
50
100
TEMPERATURE (°C)
150
0
50
100
TEMPERATURE (°C)
150
0
50
100
TEMPERATURE (°C)
150
6
5
4
3
2
1
0
–50
ALL OUTPUTS ON
V
DD
= 12V
IL = 350mA
VDD = 12V
IL = 100mA
ALL OUTPUTS OFF
0.7
0.6
0.5
-50
0
50
100
TEMPERATURE (°C)
150
0
50
100
TEMPERATURE (°C)
150
August 2001
5
CURRENT LIMIT DELAY (µS)
SATURATION VOLTAGE (V)
SUPPLY CURRENT (mA)
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
Output Saturation
Voltage vs. Temperature
7
Supply Current
vs. Temperature
20
18
16
14
12
10
8
6
V
DD
= 12V
4
2 V
DD
= 5V
0
0.3 0.4 0.5 0.6 0.7 0.8 0.9
OUTPUT CURRENT (A)
Current Shutdown
Delay vs. Output Current
MIC59P60
嵌入式系统
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