MGA-13116
High Gain, High Linearity, Very Low Noise Amplifier
Data Sheet
Description
Avago Technologies’ MGA-13116 is a two stage, easy-to-
use GaAs MMIC Low Noise Amplifier (LNA). The LNA has
low noise with good input return loss and high linearity
achieved through the use of Avago Technologies’ propri-
etary 0.25
Pm
GaAs Enhancement-mode pHEMT process.
Minimum matching needed for input, output and the
inter-stage between the two LNA.
It is designed for optimum use between 400 MHz to 1.5
GHz. For optimum performance at higher frequency from
1.5 GHz to 2.5 GHz, the MGA-13216 is recommended. Both
MGA-13116 & MGA-13216 share the same package and
pinout configuration.
Features
x
Optimum frequency of operation 400 MHz – 1.5 GHz
x
Very low noise figure
x
High gain
x
High linearity performance
x
Excellent isolation
x
GaAs E-pHEMT Technology
[1]
x
Low cost small package size: 4.0 x 4.0 x 0.85 mm
3
Specifications
900 MHz; Q1: 5 V, 55 mA (typ) Q2: 5 V, 112 mA (typ)
x
x
x
x
x
0.51 dB Noise Figure
38 dB Gain
52 dB RFoutQ1 to RFinQ2 Isolation
41.4 dBm Output IP3
23.3 dBm Output Power at 1dB gain compression
Pin Configuration and Package Marking
4.0 x 4.0 x 0.85 mm
3
16-lead QFN
13
14
15
16
AVAGO
13116
YYWW
XXXX
12
11
10
9
8
7
6
5
GND
1
2
3
4
Pin
2
Pin
3
Pin 10
Pin 11
Pin 13
Pin 16
Vbias
RFinQ1
RFoutQ2
RFoutQ2
RFinQ2
RFoutQ1
Applications
x
Low noise amplifier for cellular infrastructure including
GSM, CDMA, and W-CDMA.
x
Other very low noise applications.
All other pics
NC
–
Not Connected
TOP VIEW
BOTTOM VIEW
Simplified Schematic
Vdd1
C9
R3
C8
C10
R4
R2
C7
L3
C6
16
1
15
Note:
Package marking provides orientation and identification
“13116” = Device Part Number
“YYWW” = Work Week and Year of Manufacture
“XXXX” = Lot Number
Vdd2
C5
C4
R1
14 13
12
11
Q2
10
9
8
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 90 V
ESD Human Body Model = 300 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
C3
L1
RFIN C1
2 Q1bias
3
4
5
6
7
Q1
L2
C2
RFOUT
Notes: Enhancement mode technology employs positive gate bias,
thereby eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
MGA-13116 Absolute Maximum Rating
[1]
TA = 25° C
Symbol
Vdd1
Vdd2
Idd1
P
d
P
in,max
T
j,max
T
stg
Thermal Resistance
[3]
Units
V
V
mA
W
dBm
°C
°C
Parameter
Device Voltage
Device Voltage
Q1 Drain Current
Power Dissipation
(2)
CW RF Input Power
Junction Temperature
Storage Temperature
Absolute Maximum
5.5
5.5
90
1.02
20
150
-65 to 150
(V
dd1
=5.0V, I
dd1
=55mA, V
dd2
=5.0V,
I
dd2
=112mA)
T
jc
= 41.9°C/W
Notes:
1. Operation of this device in excess of any of
these limits may cause permanent damage.
2. Board temperature (T
c
) is 25° C. For T
c
>100° C,
derate the device power at 23.9 mW per
°C rise in board temperature adjacent to
package bottom.
3. Thermal resistance measured using Infrared
Measurement Technique.
Electrical Specifications
[1]
RF performance at Vdd1 = 5 V, V
dd2
= 5 V, 900 MHz, T
A
= 25° C, measured on the demo board.
Symbol
Idd1
Idd2
NF
Gain
OIP3
[2]
OP1dB
IRL
ORL
|S12|
|ISOL
1-2
|
Parameter and Test Condition
Current at Q1
Current at Q2
Noise Figure
Gain
Output Third Order Intercept Point
Output Power at 1 dB Gain Compression
Input Return Loss, 50
:
source
Output Return Loss, 50
:
load
Reverse Isolation
Isolation between Q1’s Output pin & Q2’s Input pin
Units
mA
mA
dB
dB
dBm
dBm
dB
dB
dB
dB
Min.
42
92
–
36.5
37.5
22
–
–
–
–
Typ.
55
112
0.51
38
41.4
23.3
-19
-12
48
52
Max.
69
131
0.85
39.5
–
–
–
–
–
–
Notes:
1. Measurements obtained using demo board described in Figure 7 with component list in Table 1. Input and Output trace loss is not de-embedded
from the measurement.
2. OIP3 test condition: f
tone1
= 900 MHz, f
tone2
= 901 MHz with input power of -29 dBm per tone.
3. Use proper bias, heatsink and derating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application
note for more details.
2
Product consistency Distribution Charts
[1,2]
LSL
USL
LSL
USL
45
50
55
60
65
100
110
120
130
Figure 1. Idd1 @ 900 MHz, Vdd1 = 5 V, LSL = 42 mA, Nominal = 55 mA,
USL = 69 mA
Figure 2. Idd2 @ 900 MHz, Vdd2 = 5 V, LSL = 92 mA, Nominal = 112 mA,
USL = 131 mA
USL
LSL
USL
0.2
0.3
0.4
0.5
0.6
0.7
0.8
37
38
39
Figure 3. Noise Figure @ 900 MHz, Vdd1 = 5 V, Vdd2 = 5 V, Nominal = 0.51 dB,
USL = 0.85 dB
Figure 4. Gain @ 900 MHz, Vdd1 = 5 V, Vdd2 = 5 V, LSL = 36.5 dB,
Nominal = 38 dB, USL = 39.5 dB
LSL
LSL
38
39
40
41
42
43
22
22.5
23
23.5
Figure 5. OIP3 @ 900 MHz, Vdd1 = 5 V, Vdd2 = 5 V, LSL = 37.5 dBm,
Nominal = 41.4 dBm
Figure 6. OP1dB @ 900 MHz, Vdd1 = 5 V, Vdd2 = 5 V, LSL = 22 dBm,
Nominal = 23.3 dBm
Notes:
1. Data sample size is 10026 samples taken from 3 different wafers. Future wafers allocated to this product may have nominal values anywhere
between the upper and lower limits.
2. Measurements are made on production test board which represents a trade-off between optimal Gain, NF, OIP3 and OP1dB. Circuit losses have
been de-embedded from actual measurements.
3
Demo Board Layout
VDD1
VDD2
GND
VBias
GND
Demo Board Schematic
Vdd1
R5
C10 C12
R2
Vdd2
GND
R4b
R4a
C9b
C9a
R3
C8
C11
C1 L1
L4
C9
R3
C8
C10
R4
R2
C7
L3
C6
16
1
15
IN
C5b
C7 L3
C5a
C4
C6 R1
C3
OUT
L2
C2
L5
C13
C5
C4
R1
14 13
12
11
Q2
10
9
8
C3
JAN 2011
AVAGO
Technologies
L1
RFIN C1
2 Q1bias
3
4
5
6
7
Q1
L2
C2
RFOUT
MANGROVE
Figure 7. Demo Board layout diagram.
Figure 8. Demo Board schematic diagram.
– Recommended PCB material is 10 mils Rogers R04350.
– Suggested component values may vary according to layout and PCB material.
Table 1. Component list for 900MHz matching
Part
C1, C6
C2
C3
C4
C5a
C7
C9a, C9b
C8, C10
L1
L2
L3
R3, R1
R2
R4b
Size
0402
0402
0402
0402
0603
0402
N/A
0402
0402
0402
0402
0402
0402
0402
Value
100pF (Murata)
12pF (Murata)
10pF (Murata)
0.1uF (Murata)
2.2uF (Murata)
33pF (Murata)
Not used
4.7uF (Murata)
18nH (Toko)
39nH (Toko)
39nH (Toko)
0 ohm (Koa)
10 ohm (Rohm)
6.8K ohm (Koa)
Detail Part Number
GRM1555C1H101JD01E
MCH155A120JK
GRM1555C1H100JZ01E
GRM155R61A104KA01D
GRM188R61A225KE34D
GRM1555C1H330JZ01E
Not used
GRM155R60E475ME760
LL1005-FHL18NJ
LL1005-FHL39NJ
LL1005-FHL39NJ
RK73Z1ELTP
MCR01J100
RM73B1E682J
Notes
DC Blocking Capacitors
DC Blocking Capacitor
Bypass Capacitor
Bypass Capacitor
Bypass Capacitor
Bypass Capacitor
Bypass Capacitor
Bypass Capacitors
Input Match for NF
Output match for Q2
Output match for Q1
Bridging Resistors
Stabilizing Resistor for Q1
Biasing Resistor for Q1
4
MGA-13116 Typical Performance in Demoboard for 900 MHz
T
A
= 25° C, V
dd1
= 5.0 V, V
dd2
= 5.0 V, I
dd1
= 55 mA, I
dd2
= 112 mA
1.2
1.0
0.8
Gain (dB)
NF
(dB)
0.6
0.4
30
0.2
0.0
300
500
700
900
1100
Frequency (MHz)
1300
1500
25
300
500
700
900
1100
Frequency (MHz)
1300
1500
35
85° C
25° C
-40°
C
45
85° C
25° C
-40°
C
40
Figure 9. NF vs Frequency and Temperature
Figure 10. Gain vs Frequency and Temperature
50
45
40
35
30
25
300
85° C
25° C
-40°
C
500
700
900
1100
Frequency (MHz)
1300
1500
OP1dB
(dBm)
OIP3
(dBm)
28
26
24
22
20
18
16
300
500
700
900
1100
Frequency (MHz)
85° C
25° C
-40°
C
1300
1500
Figure 11. OIP3 vs Frequency and Temperature
Figure 12. OP1dB vs Frequency and Temperature
60
IRL,
ORL,
Gain,
Rev
Isol (dB)
40
20
0
-20
-40
-60
0
1
2
3
Frequency (GHz)
4
S11
S22
S21
S12
5
10
9
8
7
6
5
4
3
2
1
0
85° C
25° C
-40°
C
K - factor
0
2
4
6
8
10 12
Frequency (GHz)
14
16
18
20
Figure 13. Input Return Loss, Output Return Loss, Gain, & Reverse Isolation
vs Frequency
Figure 14. K-factor vs Frequency and Temperature
5
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