MCP4706/4716/4726
8-/10-/12-Bit Voltage Output Digital-to-Analog Converter
with EEPROM and I
2
C™ Interface
Features:
• Output Voltage Resolutions:
- 12-bit:
MCP4726
- 10-bit:
MCP4716
- 8-bit:
MCP4706
• Rail-to-Rail Output
• Fast Settling Time of 6 µs (typical)
• DAC Voltage Reference Options:
- V
DD
- V
REF
Pin
• Output Gain Options:
- Unity (1x)
- 2x, only when V
REF
pin is used as voltage
source
• Nonvolatile Memory (EEPROM):
- Auto Recall of Saved DAC register setting
- Auto Recall of Saved Device Configuration
(Voltage Reference, Gain, Power-Down)
• Power-Down modes:
- Disconnects output buffer
- Selection of V
OUT
pull-down resistors
(640 kΩ, 125 kΩ, or 1 kΩ)
• Low-Power Consumption:
- Normal Operation: 210 µA typical
- Power-Down Operation: 60 nA typical
(PD1:PD0 =
11)
• Single-Supply Operation: 2.7V to 5.5V
• I
2
C™ Interface:
- Eight Available Addresses
- Standard (100 kbps), Fast (400 kbps), and
High-Speed (3.4 Mbps) modes
• Small 6-lead SOT-23 and DFN (2x2) Packages
• Extended Temperature Range: -40°C to +125°C
Package Types
MCP4706/16/26
SOT-23-6
V
OUT
1
V
SS
2
V
DD
3
6 V
REF
5 SCL
4 SDA
2x2 DFN-6*
V
REF
1
SCL
2
SDA
3
6
V
OUT
EP
7
5
V
SS
4
V
DD
* Includes Exposed Thermal Pad (EP); see
Table 3-1.
Description:
The MCP4706/4716/4726 are single channel 8-bit,
10-bit, and 12-bit buffered voltage output Digital-to-
Analog Converters (DAC) with nonvolatile memory and
an I
2
C serial interface. This family will also be referred
to as MCP47X6.
The V
REF
pin or the device V
DD
can be selected as the
DAC’s reference voltage. When V
DD
is selected, V
DD
is
connected internally to the DAC reference circuit.
When the V
REF
pin is used, the user can select the
output buffer’s gain to 1 or 2. When the gain is 2, the
V
REF
pin voltage should be limited to a maximum of
V
DD
/2.
The DAC register value and Configuration bits can be
programmed to nonvolatile memory (EEPROM). The
nonvolatile memory holds the DAC register and
Configuration bit values when the device is powered
off. A device Reset (such as a Power-on Reset) latches
these stored values into the volatile memory.
Power-Down modes enable system current reduction
when the DAC output voltage is not required. The V
OUT
pin can be configured to present a low, medium, or high
resistance load.
These devices have a two-wire I
2
C™ compatible serial
interface for standard (100 kHz), fast (400 kHz), or
High-Speed (3.4 MHz) mode.
These devices are available in small 6-pin SOT-23 and
DFN 2x2 mm packages.
Applications:
•
•
•
•
•
•
Set Point or Offset Trimming
Sensor Calibration
Low-Power Portable Instrumentation
PC Peripherals
Data Acquisition Systems
Motor Control
©
2011-2012 Microchip Technology Inc.
DS22272C-page 1
MCP4706/4716/4726
Block Diagram
V
REF
V
REF1
:V
REF0
Reference
Selection
V
DD
V
DD
V
SS
Buffer
V
RL
Gain (1x or 2x)
(G =
0
or
1)
V
OUT
PD1:PD0
Resistor Ladder
Op
Amp
I
2
C™ Interface Logic
DAC
Register
SDA
SCL
PD1:PD0
125 kΩ
640 kΩ
1 kΩ
V
W
EEPROM
Control
Logic
DS22272C-page 2
©
2011-2012 Microchip Technology Inc.
MCP4706/4716/4726
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Voltage on V
DD
with respect to V
SS
.......................................................................................................... -0.6V to +6.5V
Voltage on all pins with respect to V
SS
..............................................................................................-0.3V to V
DD
+ 0.3V
Input clamp current, I
IK
(V
I
< 0, V
I
> V
DD
) ............................................................................................................ ±20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
DD
) .................................................................................................. ±20 mA
Maximum input current source/sunk by SDA, SCL pins ..........................................................................................2 mA
Maximum output current sunk by SDA Output pin .................................................................................................25 mA
Maximum current out of V
SS
pin .............................................................................................................................50 mA
Maximum current into V
DD
pin ................................................................................................................................50 mA
Maximum current sourced by the V
OUT
pin ............................................................................................................40 mA
Maximum current sunk by the V
OUT
pin..................................................................................................................40 mA
Maximum current sunk by the V
REF
pin ...................................................................................................................40 µA
Package power dissipation (T
A
= +50°C, T
J
= +150°C)
SOT-23-6...................................................................................................................................................452 mW
DFN-6......................................................................................................................................................1098 mW
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ...............................................................................................-55°C to +125°C
ESD protection on all pins............................................................................................................................≥ 6 kV (HBM)
......................................................................................................................................................................≥ 400V (MM)
Maximum Junction Temperature (T
J
) ................................................................................................................... +150°C
† Notice:
Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
©
2011-2012 Microchip Technology Inc.
DS22272C-page 3
MCP4706/4716/4726
ELECTRICAL CHARACTERISTICS
Electrical Specifications:
Unless otherwise indicated, V
DD
= 2.7V to 5.5V, V
SS
= 0V, R
L
= 5 kΩ from V
OUT
to GND, CL = 100 pF,
T
A
= -40°C to +125°C. Typical values at +25°C.
Parameters
Power Requirements
Input Voltage
Input Current
Symbol
V
DD
I
DD
Min
2.7
—
Typical
—
210
Max
5.5
400
Units
V
µA
Conditions
—
210
400
µA
Power-Down Current
Power-On Reset
Threshold
Power-Up Ramp Rate
DC Accuracy
Offset Error
Offset Error
Temperature Coefficient
Zero-Scale Error
I
DDP
V
POR
V
RAMP
V
OS
V
OS
/°C
E
ZS
—
—
1
0.09
2.2
—
±0.02
2
—
—
0.75
µA
V
V/S
V
REF1
:V
REF0
=
00,
SCL = SDA = V
SS
, V
OUT
is unloaded,
volatile DAC Register =
0x000
V
REF1
:V
REF0
=
11,
V
REF
= V
DD
,
SCL = SDA = V
SS
, V
OUT
is unloaded,
volatile DAC Register =
0x000
PD1:PD0 =
01
(Note
6),
V
OUT
not connected
RAM retention voltage, (V
RAM
) < V
POR
(Note
1, Note 4)
Full-Scale Error
E
FS
Gain Error
(Note
2)
g
E
Gain Error Drift
Resolution
ΔG/°C
n
INL Error
(Note
7)
DNL Error
(Note
7)
Note 1:
2:
3:
4:
5:
6:
7:
INL
DNL
% of FSR Code = 0x000h
V
REF1
:V
REF0
=
00,
G =
0
—
±1
—
ppm/°C -40°C to +25°C
—
±2
—
ppm/°C +25°C to +85°C
—
0.13
2.0
LSb
MCP4706,
Code = 0x00h
—
0.52
7.7
LSb
MCP4716,
Code = 0x000h
—
2.05
30.8
LSb
MCP4726,
Code = 0x000h
—
0.3
5.2
LSb
MCP4706,
Code = 0xFFh
—
1.1
20.5
LSb
MCP4716,
Code = 0x3FFh
—
4.1
82.0
LSb
MCP4726,
Code = 0xFFFh
-2
-0.10
2
% of FSR
MCP4706,
Code = 0xFFh
V
REF1
:V
REF0
=
00,
G =
0
-2
-0.10
2
% of FSR
MCP4716,
Code = 0x3FFh
V
REF1
:V
REF0
=
00,
G =
0
-2
-0.10
2
% of FSR
MCP4726,
Code = 0xFFFh
V
REF1
:V
REF0
=
00,
G =
0
—
-3
—
ppm/°C
8
bits
MCP4706
10
bits
MCP4716
12
bits
MCP4726
-0.907 ±0.125 +0.907
LSb
MCP4706
(codes: 6 to 250)
-3.625
±0.5
+3.625
LSb
MCP4716
(codes: 25 to 1000)
-14.5
±2
+14.5
LSb
MCP4726
(codes: 100 to 4000)
-0.05 ±0.0125 +0.05
LSb
MCP4706
(codes: 6 to 250)
-0.188 ±0.05 +0.188
LSb
MCP4716
(codes: 25 to 1000)
-0.75
±0.2
+0.75
LSb
MCP4726
(codes: 100 to 4000)
This parameter is ensured by design and is not 100% tested.
This Gain error does not include Offset error. See
Section 1.0 “Electrical Characteristics”
for more details in plots.
Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device).
The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of V
DD
over time.
This parameter is ensured by characterization, and not 100% tested.
The PD1:PD0 =
10,
and ‘11’ configurations should have the same current.
V
DD
= V
REF
= 5.5V.
DS22272C-page 4
©
2011-2012 Microchip Technology Inc.
MCP4706/4716/4726
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications:
Unless otherwise indicated, V
DD
= 2.7V to 5.5V, V
SS
= 0V, R
L
= 5 kΩ from V
OUT
to GND, CL = 100 pF,
T
A
= -40°C to +125°C. Typical values at +25°C.
Parameters
Output Amplifier
Minimum Output
Voltage
Maximum Output
Voltage
Phase Margin
Slew Rate
Short Circuit Current
Settling Time
Power-Down Output
Disable Time Delay
Symbol
V
OUT(MIN)
V
OUT(MAX)
PM
SR
I
SC
t
SETTLING
T
PDD
Min
—
—
—
—
7
—
—
Typical
0.01
V
DD
–
0.04
66
0.55
15
6
1
Max
—
—
—
—
24
—
—
Units
V
V
Degree
(°)
V/µs
mA
µs
µs
Conditions
Output Amplifier’s minimum drive
Output Amplifier’s maximum drive
CL = 400 pF, RL =
∞
Power-Down Output
Enable Time Delay
T
PDE
—
10.5
—
µs
Note 3
PD1:PD0 =
00
->
11,
‘10’, or ‘01’
started from falling edge SCL at end of
ACK bit.
V
OUT
= V
OUT
- 10 mV. V
OUT
not
connected.
PD1:PD0 =
11,
‘10’, or ‘01’ -> “00”
started from falling edge SCL at end of
ACK bit.
Volatile DAC Register = FFh,
V
OUT
= 10 mV. V
OUT
not connected.
Buffered mode
Unbuffered mode
Unbuffered mode
Unbuffered mode
V
REF
= 2.048V ± 0.1V,
V
REF1
:V
REF0
=
10,
G =
0
V
REF
= 2.048V ± 0.1V,
V
REF1
:V
REF0
=
10,
G =
1
V
REF
= 2.048V ± 0.1V,
V
REF1
:V
REF0
=
10,
G =
0,
Frequency = 1 kHz
1 LSb change around major carry
(800h to 7FFh)
External Reference (V
REF
) (Note
1)
Input Range
V
REF
0.04
0
—
—
—
—
Total Harmonic
Distortion
THD
—
—
—
210
29
86.5
67.7
-73
Input Impedance
Input Capacitance
-3 dB Bandwidth
R
VREF
C_
REF
V
DD
-
0.04
V
DD
—
—
—
—
—
V
V
kΩ
pF
kHz
kHz
dB
Dynamic Performance (Note
1)
Major Code Transition
Glitch
Digital Feedthrough
Note 1:
2:
3:
4:
5:
6:
7:
—
—
45
<10
—
—
nV-s
nV-s
This parameter is ensured by design and is not 100% tested.
This Gain error does not include Offset error. See
Section 1.0 “Electrical Characteristics”
for more details in plots.
Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device).
The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of V
DD
over time.
This parameter is ensured by characterization, and not 100% tested.
The PD1:PD0 =
10,
and ‘11’ configurations should have the same current.
V
DD
= V
REF
= 5.5V.
©
2011-2012 Microchip Technology Inc.
DS22272C-page 5
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