MCP2515
Stand-Alone CAN Controller with SPI Interface
Features:
• Implements CAN V2.0B at 1 Mb/s:
- 0 – 8 byte length in the data field
- Standard and extended data and remote
frames
• Receive Buffers, Masks and Filters:
- Two receive buffers with prioritized message
storage
- Six 29-bit filters
- Two 29-bit masks
• Data Byte Filtering on the First Two Data Bytes
(applies to standard data frames)
• Three Transmit Buffers with Prioritization and
Abort Features
• High-Speed SPI Interface (10 MHz):
- SPI modes
0,0
and
1,1
• One-Shot mode Ensures Message Transmission
is Attempted Only One Time
• Clock Out Pin with Programmable Prescaler:
- Can be used as a clock source for other
device(s)
• Start-of-Frame (SOF) Signal is Available for
Monitoring the SOF Signal:
- Can be used for time-slot-based protocols
and/or bus diagnostics to detect early bus
degradation
• Interrupt Output Pin with Selectable Enables
• Buffer Full Output Pins Configurable as:
- Interrupt output for each receive buffer
- General purpose output
• Request-to-Send (RTS) Input Pins Individually
Configurable as:
- Control pins to request transmission for each
transmit buffer
- General purpose inputs
• Low-Power CMOS Technology:
- Operates from 2.7V – 5.5V
- 5 mA active current (typical)
- 1 µA standby current (typical) (Sleep mode)
• Temperature Ranges Supported:
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
Description
Microchip Technology’s MCP2515 is a stand-alone
Controller Area Network (CAN) controller that
implements the CAN specification, version 2.0B. It is
capable of transmitting and receiving both standard
and extended data and remote frames. The MCP2515
has two acceptance masks and six acceptance filters
that are used to filter out unwanted messages, thereby
reducing the host MCU’s overhead. The MCP2515
interfaces with microcontrollers (MCUs) via an industry
standard Serial Peripheral Interface (SPI).
Package Types
18-Lead PDIP/SOIC
TXCAN
RXCAN
CLKOUT/SOF
TX0RTS
TX1RTS
TX2RTS
OSC2
OSC1
Vss
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
TXCAN
18
17
16
V
DD
RESET
CS
SO
SI
SCK
INT
RX0BF
RX1BF
V
DD
RESET
CS
SO
SI
NC
SCK
INT
RX0BF
RX1BF
MCP2515
RESET
RX1BF
V
DD
15
14
13
12
11
10
20
19
18
17
16
15
14
13
12
11
20-LEAD TSSOP
TXCAN
RXCAN
CLKOUT/SOF
TX0RTS
TX1RTS
NC
TX2RTS
OSC2
OSC1
V
SS
20 19 18 17 16
CLKOUT 1
TX0RTS 2
TX1RTS 3
NC 4
TX2RTS 5
6
OSC2
* Includes Exposed Thermal
Pad (EP); see
Table 1-1.
7
OSC1
8
GND
9 10
RX0BF
15 SO
EP
21
14 SI
13 NC
12 SCK
11 INT
2003-2012 Microchip Technology Inc.
DS21801G-page 1
CS
MCP2515
20-Lead 4x4 QFN*
RXCAN
MCP2515
MCP2515
NOTES:
DS21801G-page 2
2003-2012 Microchip Technology Inc.
MCP2515
1.0
DEVICE OVERVIEW
1.2
Control Logic
The MCP2515 is a stand-alone CAN controller
developed to simplify applications that require
interfacing with a CAN bus. A simple block diagram of
the MCP2515 is shown in
Figure 1-1.
The device
consists of three main blocks:
1.
The CAN module, which includes the CAN
protocol engine, masks, filters, transmit and
receive buffers.
The control logic and registers that are used to
configure the device and its operation.
The SPI protocol block.
The control logic block controls the setup and operation
of the MCP2515 by interfacing to the other blocks in
order to pass information and control.
Interrupt pins are provided to allow greater system
flexibility. There is one multi-purpose interrupt pin (as
well as specific interrupt pins) for each of the receive
registers that can be used to indicate a valid message
has been received and loaded into one of the receive
buffers. Use of the specific interrupt pins is optional.
The general purpose interrupt pin, as well as status
registers (accessed via the SPI interface), can also be
used to determine when a valid message has been
received.
Additionally, there are three pins available to initiate
immediate transmission of a message that has been
loaded into one of the three transmit registers. Use of
these pins is optional, as initiating message
transmissions can also be accomplished by utilizing
control registers, accessed via the SPI interface.
2.
3.
An example system implementation using the device is
shown in
Figure 1-2.
1.1
CAN Module
The CAN module handles all functions for receiving
and transmitting messages on the CAN bus. Messages
are transmitted by first loading the appropriate
message buffer and control registers. Transmission is
initiated by using control register bits via the SPI
interface or by using the transmit enable pins. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against the user-
defined filters to see if it should be moved into one of
the two receive buffers.
1.3
SPI Protocol Block
The MCU interfaces to the device via the SPI interface.
Writing to, and reading from, all registers is
accomplished using standard SPI read and write
commands, in addition to specialized SPI commands.
FIGURE 1-1:
CAN Module
BLOCK DIAGRAM
RXCAN
CAN
Protocol
Engine
TXCAN
TX and RX Buffers
Masks and Filters
SPI
Interface
Logic
CS
SCK
SI
SO
SPI
Bus
Control Logic
OSC1
OSC2
CLKOUT
Timing
Generation
INT
RX0BF
RX1BF
TX0RTS
Control
and
Interrupt
Registers
TX1RTS
TX2RTS
RESET
2003-2012 Microchip Technology Inc.
DS21801G-page 3
MCP2515
FIGURE 1-2:
EXAMPLE SYSTEM IMPLEMENTATION
Node
Controller
SPI
Node
Controller
SPI
Node
Controller
SPI
MCP2515
TX
XCVR
RX
MCP2515
TX
XCVR
RX
MCP2515
TX
XCVR
RX
CANH
CANL
TABLE 1-1:
Name
TXCAN
RXCAN
CLKOUT
TX0RTS
TX1RTS
TX2RTS
OSC2
OSC1
V
SS
RX1BF
RX0BF
INT
SCK
SI
SO
CS
RESET
V
DD
NC
Note:
PINOUT DESCRIPTION
TSSOP
Pin #
QFN
Pin #
I/O/P
Type
PDIP/
SOIC
Pin #
Description
Transmit output pin to CAN bus
Receive input pin from CAN bus
Clock output pin with programmable
prescaler
Alternate Pin Function
—
—
Start-of-Frame signal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
—
1
2
3
4
5
7
8
9
10
11
12
13
14
16
17
18
19
20
6,15
19
20
1
2
3
5
6
7
8
9
10
11
12
14
15
16
17
18
4,13
O
I
O
I
I
I
O
I
P
O
O
O
I
I
O
I
I
P
—
Transmit buffer TXB0 request-to-send. General purpose digital input.
100 kinternal pull-up to V
DD
100 kinternal pull-up to V
DD
Transmit buffer TXB1 request-to-send. General purpose digital input.
100 kinternal pull-up to V
DD
100 kinternal pull-up to V
DD
Transmit buffer TXB2 request-to-send. General purpose digital input.
100 kinternal pull-up to V
DD
100 kinternal pull-up to V
DD
Oscillator output
Oscillator input
Ground reference for logic and I/O
pins
Receive buffer RXB1 interrupt pin or
general purpose digital output
Receive buffer RXB0 interrupt pin or
general purpose digital output
Interrupt output pin
Clock input pin for SPI interface
Data input pin for SPI interface
Data output pin for SPI interface
Chip select input pin for SPI interface
Active-low device Reset input
Positive supply for logic and I/O pins
No internal connection
—
External clock input
—
General purpose digital output
General purpose digital output
—
—
—
—
—
—
—
—
Type Identification: I = Input; O = Output; P = Power
DS21801G-page 4
2003-2012 Microchip Technology Inc.
MCP2515
1.4
Transmit/Receive Buffers/Masks/
Filters
The MCP2515 has three transmit and two receive
buffers, two acceptance masks (one for each receive
buffer) and a total of six acceptance filters.
Figure 1-3
shows a block diagram of these buffers and their
connection to the protocol engine.
FIGURE 1-3:
CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM
BUFFERS
Acceptance Mask
RXM1
Acceptance Filter
RXF2
TXB0
MESSAGE
TXREQ
ABTF
MLOA
TXERR
TXB1
MESSAGE
TXREQ
ABTF
MLOA
TXERR
TXB2
MESSAGE
TXREQ
ABTF
MLOA
TXERR
A
c
c
e
p
t
Acceptance Mask
RXM0
Acceptance Filter
RXF0
Acceptance Filter
RXF1
R
X
B
0
Acceptance Filter
RXF3
Acceptance Filter
RXF4
Acceptance Filter
RXF5
R
X
B
1
A
c
c
e
p
t
Message
Queue
Control
Identifier
M
A
B
Identifier
Transmit Byte Sequencer
Data Field
Data Field
PROTOCOL
ENGINE
Receive
Error
Counter
Transmit
Error
Counter
REC
TEC
ErrPas
BusOff
Transmit<7:0>
Shift<14:0>
{Transmit<5:0>, Receive<8:0>}
Comparator
Receive<7:0>
CRC<14:0>
Protocol
Finite
State
Machine
SOF
Transmit
Logic
Bit
Timing
Logic
Clock
Generator
TX
RX
Configuration
Registers
2003-2012 Microchip Technology Inc.
DS21801G-page 5
FPGA/CPLD
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