Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MCF53017
Rev. 3, 8/2009
MCF53017
LQFP–208
28 x 28
MAPBGA–256
17 x 17
MCF5301x Data Sheet
Features
• Version 3 ColdFire
®
core with EMAC
• Up to 211 Dhrystone 2.1 MIPS @ 240 MHz
• 16 KBytes unified instruction/data cache
• 128 KBytes internal SRAM with standby power supply
support
• Crossbar switch technology (XBS) for concurrent access to
peripherals or RAM from multiple bus masters
• Enhanced Secure Digital Host Controller (eSDHC)
– Supports CE-ATA, SD Memory, miniSD Memory,
SDIO, miniSDIO, SD Combo, MMC, MMC plus, MMC
4x, and MMC RS cards
• Two ISO7816 smart card interfaces
• IC identification module
• Voice-band audio codec with integrated speaker,
microphone, headphone, and handset amplifiers
• 16- or 32-bit SDR, 16-bit DDR/mobile-DDR SDRAM
controller
• USB 2.0 On-the-Go controller
• USB host controller
• 2 10/100 Ethernet MACs
• Coprocessor for acceleration of the DES, 3DES, AES,
MD5, and SHA-1 algorithms
• Random number generator
• 16-channel DMA controller
• Synchronous serial interface
• 4 periodic interrupt timers
• 4 32-bit timers with DMA support
• Real-time clock (RTC) module with standby support
• DMA-supported serial peripheral interface (DSPI)
• 3 UARTs
• I
2
C bus interface
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Preliminary—Subject to Change Without Notice
Table of Contents
1
2
3
MCF5301x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5
3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.3 Supply Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . .6
3.3.1 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . .7
3.3.2 Power Down Sequence . . . . . . . . . . . . . . . . . . . .7
3.4 Power Consumption Specifications. . . . . . . . . . . . . . . . .8
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .9
4.1 Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.2 Pinout—208 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3 Pinout–256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . .18
Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .19
5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .20
5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .21
5.4.1 PLL Power Filtering . . . . . . . . . . . . . . . . . . . . . .22
5.4.2 USB Power Filtering. . . . . . . . . . . . . . . . . . . . . .22
5.4.3 Supply Voltage Sequencing and
Separation Cautions . . . . . . . . . . . . . . . . . . . . .23
5.5 Oscillator and PLL Electrical Characteristics . . . . . . . .24
5.6 External Interface Timing Characteristics . . . . . . . . . . .25
5.6.1 FlexBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.7 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.7.1 SDR SDRAM AC Timing Characteristics. . . . . .27
5.7.2 DDR SDRAM AC Timing Characteristics . . . . .30
5.8 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . .32
5.9 Reset and Configuration Override Timing. . . . . . . . . . .33
5.10 USB On-The-Go . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.11 SSI Timing Specifications . . . . . . . . . . . . . . . . . . . . . .
5.12 I
2
C Input/Output Timing Specifications . . . . . . . . . . . .
5.13 Fast Ethernet AC Timing Specifications . . . . . . . . . . .
5.13.1 Receive Signal Timing Specifications . . . . . . .
5.13.2 Transmit Signal Timing Specifications . . . . . . .
5.13.3 Asynchronous Input Signal Timing
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
5.13.4 MII Serial Management Timing Specifications .
5.14 32-Bit Timer Module Timing Specifications . . . . . . . . .
5.15 DSPI Timing Specifications . . . . . . . . . . . . . . . . . . . . .
5.16 eSDHC Electrical Specifications . . . . . . . . . . . . . . . . .
5.16.1 eSDHC Timing . . . . . . . . . . . . . . . . . . . . . . . . .
5.16.2 eSDHC Electrical DC Characterisics . . . . . . . .
5.17 SIM Electrical Specifications . . . . . . . . . . . . . . . . . . . .
5.17.1 General Timing Requirements . . . . . . . . . . . . .
5.17.2 Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . .
5.17.3 Power Down Sequence . . . . . . . . . . . . . . . . . .
5.18 IIM/Fusebox Electrical Specifications . . . . . . . . . . . . .
5.19 Voice Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.19.1 Voice Codec ADC Specifications . . . . . . . . . . .
5.19.2 Voice Codec DAC Specifications . . . . . . . . . . .
5.20 Integrated Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . .
5.20.1 Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . .
5.20.2 Handset Amplifier . . . . . . . . . . . . . . . . . . . . . . .
5.20.3 Headphone Amplifier . . . . . . . . . . . . . . . . . . . .
5.20.4 Microphone Amplifier . . . . . . . . . . . . . . . . . . . .
5.21 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . .
5.22 Debug AC Timing Specifications . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
35
37
37
37
38
38
39
39
41
41
42
43
43
44
45
46
46
47
51
55
55
56
57
57
58
60
61
61
62
4
5
6
7
8
MCF5301x Data Sheet, Rev. 3
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF53017
Version 3 ColdFire Core
16K
Instruction/
Data
Cache
JTAG
Oscillator
PLL
EMAC
BDM
2 FECs
USB Host
128K
SRAM
Hardware
Divide
CAU
eDMA
eSDHC
USB OTG
Crossbar Switch (XBS)
Splitter
Peripheral Bridge
Codec
IIM
Smart Card
Interface
I
2
C
RTC &
Oscillator
4 DMA
Timers
DSPI
FlexBus
GPIO
SDRAM
Controller
SSI
RNG
2 INTCs
2 EPORTs
3 UARTs
4 PITs
LEGEND
BDM
CAU
DSPI
eDMA
eSDHC
EMAC
EPORT
FEC
GPIO
I
2
C
– Background debug module
– Cryptography acceleration unit
– DMA serial peripheral interface
– Enhanced direct memory access module
– Enhanced Secure Digital host controller
– Enchanced multiply-accumulate unit
– Edge port module
– Fast Ethernet Controller
– General purpose input/output module
– Inter-Integrated Circuit
IIM
INTC
JTAG
PCI
PIT
PLL
RNG
RTC
SSI
USB OTG
–
IC identification module
–
Interrupt controller
– Joint Test Action Group interface
– Peripheral Component Interconnect
– Programmable interrupt timers
– Phase locked loop module
– Random number generator
– Real time clock
– Synchronous serial interface
– Universal Serial Bus On-the-Go controller
MCF5301x Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
MCF5301x Family Comparison
1
MCF5301x Family Comparison
Table 1. MCF5301x Family Configurations
MCF53010
MCF53011
MCF53012
MCF53013
MCF53014
MCF53015
MCF53016
MCF53017
•
•
•
•
•
•
•
•
•
•
•
•
2
3
•
•
•
4
•
4
•
2
The following table compares the various device derivatives available within the MCF5301x family.
Module
Version 3 ColdFire Core with EMAC (enhanced
multiply-accumulate unit)
Core (system) clock
Peripheral and external bus clock
(Core clock
÷
3)
Performance (Dhrystone/2.1 MIPS)
Unified data/instruction cache
Static RAM (SRAM)
Voice-over-IP software
Cryptography acceleration unit (CAU)
Random number generator
Smart card interface (SIM)
Voice-band audio codec
Integrated audio amplifiers
IC identification module (IIM)
Enhanced Secure Digital host controller (eSDHC)
SDR/DDR SDRAM controller
FlexBus external interface
USB 2.0 On-the-Go
USB 2.0 Host
Synchronous serial interface (SSI)
Fast Ethernet controller (FEC)
UARTs
I
2
C
DSPI
Real-time clock
32-bit DMA timers
Watchdog timer (WDT)
Periodic interrupt timers (PIT)
Edge port module (EPORT)
Interrupt controllers (INTC)
•
•
•
•
•
•
•
up to 240 MHz
up to 80 MHz
up to 211
16 Kbytes
128 Kbytes
—
—
—
—
•
•
1 port
•
—
•
—
•
—
•
—
2 Kbits
•
•
•
•
—
•
2
3
•
•
•
4
•
4
•
2
•
•
•
•
—
•
2
3
•
•
•
4
•
4
•
2
•
•
•
•
—
•
2
3
•
•
•
4
•
4
•
2
•
•
•
•
—
•
2
3
•
•
•
4
•
4
•
2
•
•
•
•
•
•
2
3
•
•
•
4
•
4
•
2
•
•
•
•
•
•
2
3
•
•
•
4
•
4
•
2
•
•
•
•
•
•
2
3
•
•
•
4
•
4
•
2
•
•
•
•
•
—
—
•
•
•
—
—
—
—
•
•
•
—
—
2 ports
•
•
MCF5301x Data Sheet, Rev. 3
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Ordering Information
Table 1. MCF5301x Family Configurations (continued)
MCF53010
MCF53011
MCF53012
MCF53013
MCF53014
MCF53015
MCF53016
MCF53017
•
•
•
5
Module
16-channel direct memory access (DMA)
General purpose I/O Module (GPIO)
JTAG - IEEE
®
1149.1 Test Access Port
Package
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
208 LQFP
256 MAPBGA
2
Ordering Information
Table 2. Orderable Part Numbers
Freescale Part Number
MCF53010CQT240
MCF53011CQT240
MCF53012CQT240
MCF53013CQT240
MCF53014CMJ240J
MCF53015CMJ240J
MCF53016CMJ240J
MCF53017CMJ240J
Description
MCF53010 Microprocessor
MCF53011 Microprocessor
208 LQFP
MCF53012 Microprocessor
MCF53013 Microprocessor
240 MHz
MCF53014 Microprocessor
MCF53015 Microprocessor
256 MAPBGA
MCF53016 Microprocessor
MCF53017 Microprocessor
–40
°
to +85
°
C
Package
Speed
Temperature
3
3.1
Hardware Design Considerations
PLL Power Filtering
To further enhance noise isolation, an external filter is strongly recommended for PLL analog V
DD
pins. The filter shown in
Figure 1
should be connected between the board IV
DD
and the PLLV
DD
pins. The resistor and capacitors should be placed as
close to the dedicated PV
DD
pin as possible. The 10-ohm resistor in the given filter is required, do not implement the filter circuit
using only capacitors. The PV
DD
pins draw very little current, so concerns regarding voltage loss across the 10-ohm resistor are
not valid.
10
Ω
Board IV
DD
10 µF
0.1 µF
PLL V
DD
Pin
GND
Figure 1. System PLL V
DD
Power Filter
MCF5301x Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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