HD151012
8-bit Binary Programmable Counter with Synchronous Preset
Enable
ADE-205-132 (Z)
Preliminary
1st. Edition
Mar. 1996
Description
The HD151012 has 8-bit binary down counter and D-type Flip Flop. The counter can set up to max 256
counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock
pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose
data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid crystal
and general-use divider.
Features
•
High speed operation
tpd (CLK or
CLK
to Q) = 35 ns (typ)
•
High output current
Fanout of 10 LS TTL Loads
•
Wide operating voltage
V
CC
= 2 to 6 V
•
Low supply current (Ta = 25°C)
I
CC
(Static) = 4 µA (max)
HD151012
Function Table
Control Inputs
CLR
H
X
L
H
PR
H
X
H
L
SPE
H
L
—
—
Mode
Generally count
Synchronous preset
Initialize of Q output
Initialize of Q output
Operation Description
Down count at the rise edge of clock (CLK)
Down count at the fall edge of clock (CLK)
Jn data is preset at the rise of clock (CLK), the fall
of clock (CLK)
Initialize of Q = “L”
Initialize of Q = “H”
Notes: 1. Synchronous preset (SPE) input can set max 256 down counts.
2. When the count value is 0, the next clock pulse presets the data to invert the output.
3. CLR and PR inputs initialize output state.
H : High level
L : Low level
X : Immaterial
— : Irrespective of condition
Pin Arrangement
J0 1
J1 2
J2 3
J3 4
J4 5
J5 6
J6 7
GND 8
16 V
CC
15 CLK
14 CLK
13 Q
12 PR
11 SPE
10 CLR
9 J7
(Top view)
2
HD151012
Pin Description
Pin Name
Input pins
J0 to J7
CLK,
CLK
SPE
PR
CLR
Output pins
Q
Pin Description
Count data input for option
Clock inputs
Preset input for Jn data
Preset input for D-type Flip Flop (Initialize “L” at Q output)
Clear input for D-type Flip Flop (Initialize “H” at Q output)
Output for D-type Flip Flop
CLK : Rise edge trigger
CLK
: Fall edge trigger
Absolute Maximum Ratings
Item
Supply voltage
Input / output voltage
VCC, GND current
Output current / pin
Power dissipation
Storage temperature
Input diode current
Output diode current
Symbol
V
CC
V
IN
/V
OUT
I
CC
, IGND
I
OUT
P
T
Tstg
I
IK
I
OK
Ratings
–0.5 to 7.0
–0.5 to V
CC
+0.5
±50
±25
500
–65 to 150
±20
±20
Unit
V
V
mA
mA
mW
°C
mA
mA
Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
2. All voltage values except for differential input voltage are with respect to network ground
terminal.
3
HD151012
Recommended Operating Conditions
Item
Supply voltage
Input/output voltage
Operating temperature
Input rise/fall time*
1
V
CC
= 2.5 V
V
CC
= 4.5 V
V
CC
= 5.5 V
Note:
Symbol
V
CC
V
IN
/
OUT
Topr
t
r
, t
f
Min
2
0
–40
0
0
0
Typ
—
—
—
—
—
—
Max
6
V
CC
+85
1000
500
400
Unit
V
V
°C
ns
1. This item guarantees maximum limit when one input switches.
Logic Diagram
J0
J1
J2
J3
J4
J5
J6
J7
J0
8-bit binary counter
J1
J2
J3
J4
J5
J6
J7
CLK
CLK
CLK
PR
PR
D
CO
SPE
CK
CLR
SPE
CLR
Q
Q
Q
4
HD151012
Electrical Characteristics
Ta = 25°C
Item
High level input
voltage
Symbol
V
IH
V
CC
2.0
4.5
6.0
2.0
4.5
6.0
Low level input
voltage
V
IL
2.0
4.5
6.0
2.0
4.5
6.0
High level output
voltage
V
OH
2.0
4.5
6.0
4.5
6.0
Low level output
voltage
V
OL
2.0
4.5
6.0
4.5
6.0
Input capacitance
Supply current
I
IN
I
CC
6.0
6.0
Min
1.5
3.15
4.2
1.5
3.15
4.2
—
—
—
—
—
—
1.9
4.4
5.9
4.18
5.68
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
2.0
4.5
6.0
4.31
5.80
0.0
0.0
0.0
0.17
0.18
—
—
Max
—
—
—
—
—
—
0.5
1.35
1.8
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
Ta =
–40 to 85°C
Min
1.5
3.15
4.2
1.5
3.15
4.2
—
—
—
—
—
—
1.9
4.4
5.9
4.13
5.63
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
0.5
1.35
1.8
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.33
0.33
±1.0
40.0
mA
mA
I
OL
= 4 mA
I
OL
= 5.2 mA
V
IN
= V
CC
or GND
V
IN
= V
CC
or GND
V
V
IN
=
V
IH
or V
IL
I
OH
= –4 mA
I
OH
= –5.2 mA
I
OL
= 20 mA
V
V
IN
=
V
IH
or V
IL
I
OH
= –20 mA
V
J0 to J7
SPE
PR, CLR
CLK,
CLK
Unit
V
Test Conditions
J0 to J7
SPE
PR, CLR
CLK,
CLK
5
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