Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (TQFN) (soldering, 10s) ....................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (B
JA
) ....65.1NC/W
Junction-to-Case Thermal Resistance (B
JC
) ...........5.4NC/W
WLP
Junction-to-Ambient Thermal Resistance (B
JA
) .......52NC/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
CC
= 1.62V to 3.6V, T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25NC.) (Notes 2, 3)
PARAMETER
Operating Supply Voltage
Second Logic Supply
Operating Supply Current
Sleep-Mode Supply Current
POR Threshold
GPIO SPECIFICATIONS
External Supply Voltage
PORT15–PORT12 (LED Drivers)
LED Port-to-Port Sink Current
Variation
10mA Port Sink Current
PORT15–PORT12
20mA Port Sink Current
PORT15–PORT12
Input High Voltage PORT_
Input Low Voltage PORT_
Input Leakage Current
PORT11–PORT0
Input Leakage Current
PORT15–PORT12
I
OL
V
LED
V
CC
= 3.3V, V
OL
= 1V, T
A
= +25NC,
10mA output mode
V
OL
= 1V
V
OL
= 0.5V
I
OL
V
IH
V
IL
I
LEAKAGE
I
LEAKAGE
V
OL
= 1V
V
OL
= 0.5V
T
A
= +25NC
V
CC
= 3.3V
V
CC
= 3.6V, T
A
= +25NC
T
A
= +25NC
V
CC
= 3.3V
V
CC
= 3.6V, T
A
= +25NC
0.7
O
V
S
0.3
O
V
S
-2
-1
+2
+1
18.13
18.47
20
19.05
V
V
FA
FA
8.6
9.04
10
9.5
21.52
21.34
mA
Q1.5
5
Q2.4
11.4
10.96
mA
V
%
SYMBOL
V
CC
V
LA
I
CC
I
SL
V
POR
Oscillator running
Not using GPO or LED configuration
CONDITIONS
MIN
1.62
V
CC
TYP
3.3
3.3
50
1.8
1.2
MAX
3.6
3.6
65
3
UNITS
V
V
FA
FA
V
V
S
= V
CC
or V
LA
depending on
reference logic level setting
Input voltage = V
CC
or V
GND
Input voltage = 5V
Maxim Integrated Products
2
MAX7304
I
2
C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 1.62V to 3.6V, T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25NC.) (Notes 2, 3)
PARAMETER
Input Capacitance PORT_
Output Low Voltage PORT_
SYMBOL
C
IN
V
OL
V
CC
= 1.62V and I
SINK
= 2.5mA
V
CC
= 1.62V and I
SINK
= 5mA
V
CC
= 1.62V and I
SOURCE
= 2.5mA
V
OH
V
CC
= 1.62V and I
SOURCE
= 5mA
V
OL
f
PWM
V
IH
V
IL
I
LEAKAGE
V
OL
C
IN
Input voltage = 5.5V or V
GND
I
SINK
= 6mA
(Notes 4, 5)
-1
I
SINK
= 6mA
Derived from oscillator clock
500
V
CC
-
120
V
CC
-
250
CONDITIONS
MIN
TYP
20
50
80
V
CC
-
40
V
CC
-
70
0.6
100
250
MAX
UNITS
pF
mV
Output High Voltage
COL3–COL0, ROW_
Output Logic-Low Voltage
(INT)
PWM Frequency
Input High Voltage
SDA, SCL, AD0
Input Low Voltage
SDA, SCL, AD0
Input Leakage Current
SDA, SCL, AD0
Output Logic-Low Voltage
SDA
Input Capacitance
SDA, SCL, AD0
I
2
C TIMING SPECIFICATIONS
SCL Serial-Clock Frequency
Bus Free Time Between a STOP
and START Condition
Hold Time (Repeated) START
Condition
Repeated START Condition
Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Signal,
Transmitting
SERIAL-INTERFACE SPECIFICATIONS
mV
V
Hz
0.7
O
V
CC
0.3
O
V
CC
+1
0.6
10
V
V
FA
V
pF
f
SCL
t
BUF
t
HD, STA
t
SU, STA
t
SU, STO
t
HD, DAT
t
SU, DAT
t
LOW
t
HIGH
t
R
t
F
t
F, TX
Bus timeout enabled
Bus timeout disabled
0.05
0
1.3
0.6
0.6
0.6
400
400
kHz
Fs
Fs
Fs
Fs
(Note 6)
100
1.3
0.7
(Notes 4, 5)
(Notes 4, 5)
(Notes 4, 7)
20 +
0.1C
B
20 +
0.1C
B
20 +
0.1C
B
0.9
Fs
ns
Fs
Fs
300
300
250
ns
ns
ns
Maxim Integrated Products
3
MAX7304
I
2
C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 1.62V to 3.6V, T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25NC.) (Notes 2, 3)
PARAMETER
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus Line
Bus Timeout
ESD PROTECTION
PORT_
All Other Pins
Note
Note
Note
Note
Note
2:
3:
4:
5:
6:
IEC 61000-4-2 Air-Gap Discharge
IEC 61000-4-2 Contact Discharge
Human Body Model
Q14
Q8
Q1.5
kV
kV
SYMBOL
t
SP
C
B
t
TIMEOUT
(Notes 4, 8)
(Note 4)
14
19
CONDITIONS
MIN
TYP
MAX
50
400
27
UNITS
ns
pF
ms
All parameters are tested at T
A
= +25NC. Specifications over temperature are guaranteed by design.
All digital inputs at V
CC
or GND.
Guaranteed by design.
C
B
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.8V and 2.1V.
A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 7:
I
SINK
= 6mA. CB = total capacitance of one bus line in pF. t
R
and t
F
measured between 0.8V and 2.1V.
Note 8:
Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
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