19-2739; Rev 4; 12/09
Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD
Protection Arrays for High-Speed Data Interfaces
General Description
The MAX3202E/MAX3203E/MAX3204E/MAX3206E are
low-capacitance ±15kV ESD-protection diode arrays
designed to protect sensitive electronics attached to
communication lines. Each channel consists of a pair of
diodes that steer ESD current pulses to V
CC
or GND.
The MAX3202E/MAX3203E/MAX3204E/MAX3206E pro-
tect against ESD pulses up to ±15kV Human Body
Model, ±8kV Contact Discharge, and ±15kV Air-Gap
Discharge, as specified in IEC 61000-4-2. These
devices have a 5pF capacitance per channel, making
them ideal for use on high-speed data I/O interfaces.
The MAX3202E is a two-channel device intended for USB
and USB 2.0 applications. The MAX3203E is a triple-ESD
structure intended for USB On-the-Go (OTG) and video
applications. The MAX3204E is a quad-ESD structure
designed for Ethernet and FireWire
®
applications, and
the MAX3206E is a six-channel device designed for
cell phone connectors and SVGA video connections.
All devices are available in tiny 4-bump (1.05mm x
1.05mm) WLP, 6-bump (1.05mm x 1.57mm) UCSP™,
9-bump (1.52mm x 1.52mm) WLP, 6-pin (3mm x 3mm)
TDFN, and 12-pin (4mm x 4mm) TQFN packages and
are specified for -40°C to +85°C operation.
Features
♦
High-Speed Data Line ESD Protection
±15kV—Human Body Model
±8kV—IEC 61000-4-2, Contact Discharge
±15kV—IEC 61000-4-2, Air-Gap Discharge
♦
Tiny UCSP/WLP Package Available
♦
Low 5pF Input Capacitance
♦
Low 1nA (max) Leakage Current
♦
Low 1nA Supply Current
♦
+0.9V to +5.5V Supply Voltage Range
♦
2-, 3-, 4-, or 6-Channel Devices Available+
MAX3202E/MAX3203E/MAX3204E/MAX3206E
Ordering Information
PART
MAX3202EEWS+T
MAX3202EETT+T
MAX3203EEBT-T
MAX3203EETT+T
MAX3204EEWT+T
MAX3204EETT+T
MAX3206EEWL+T
MAX3206EETC+
PIN-PACKAGE
4-WLP
6-TDFN-EP**
6-UCSP*
6-TDFN-EP**
6-WLP
6-TDFN-EP**
9-WLP
12-TQFN-EP**
TOP MARK
+AA
+ADQ
+ABA
+ADO
+AL
+ADP
+AQ
+AACA
Applications
USB
USB 2.0
Ethernet
FireWire
Video
Cell Phones
SVGA Video Connections
Selector Guide
PART
MAX3202EEWS+T
MAX3202EETT-T
MAX3203EEBT-T
MAX3203EETT-T
MAX3204EEBT-T
MAX3204EETT-T
MAX3206EEBL-T
MAX3206EETC
ESD-PROTECTED
I/O PORTS
2
2
3
3
4
4
6
6
*UCSP
reliability is integrally linked to the user’s assembly
methods, circuit board material, and environment. Refer to the
UCSP Reliability Notice in the UCSP Reliability section for more
information.
**EP
= Exposed pad.
Note:
All devices operate over -40°C to +85°C temperature
range.
+Denotes
a lead(Pb)-free/RoHS-compliant package.
Typical Operating Circuit
V
CC
V
CC
0.1µF
0.1µF
PROTECTED
CIRCUIT
I/0
I/0_
Pin Configurations appear at end of data sheet.
FireWire is a registered trademark of Apple Computer, Inc.
UCSP is a trademark of Maxim Integrated Products, Inc.
MAX3202E
MAX3204E
MAX3206E
MAX3208E
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD
Protection Arrays for High-Speed Data Interfaces
MAX3202E/MAX3203E/MAX3204E/MAX3206E
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND ...........................................................-0.3V to +7.0V
I/O_ to GND ................................................-0.3V to (V
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
2
×
2 WLP (derate 11.5mW/°C above +70°C)...............920mW
3
×
2 UCSP (derate 3.4mW/°C above +70°C) ..............273mW
3
×
2 WLP (derate 12.3mW/°C above +70°C)...............984mW
3
×
3 WLP (derate 14.1mW/°C above +70°C).............1128mW
6-Pin TDFN (derate 24.4mW/°C above +70°C) ..........1951mW
12-Pin TQFN (derate 16.9mW/°C above +70°C) ........1349mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature .....................................................+150°C
Bump Temperature (soldering) (Note 1)
Infrared (15s) ................................................................+220°C
Vapor Phase (60s) ........................................................+215°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1:
The UCSP devices are constructed using a unique set of packaging techniques that impose a limit on the thermal profile the
device can be exposed to during board-level solder attach and rework. This limit permits the use of only the solder profiles
recommended in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and Convection
Reflow. Preheating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +5V ±5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
CC
= +5V and T
A
= +25°C.) (Note 2)
PARAMETER
Supply Voltage
Supply Current
Diode Forward Voltage
SYMBOL
V
CC
I
CC
V
F
I
F
= 10mA
T
A
= +25°C, ±15kV
Human Body Model,
I
F
= 10A
Channel Clamp Voltage
(Note 3)
V
C
T
A
= +25°C, ±8kV
Contact Discharge
(IEC 61000-4-2), I
F
= 24A
T
A
= +25°C, ±15kV
Air-Gap Discharge
(IEC 61000-4-2), I
F
= 45A
Channel Leakage Current
Channel Input Capacitance
ESD PROTECTION
Human Body Model
IEC 61000-4-2
Contact Discharge
IEC 61000-4-2
Air-Gap Discharge
±15
±8
±15
kV
kV
kV
T
A
= 0°C to +50°C (Note 4)
V
CC
= 5V, bias of V
CC
/2
Positive transients
Negative transients
Positive transients
Negative transients
Positive transients
Negative transients
-1
5
0.65
CONDITIONS
MIN
0.9
1
TYP
MAX
5.5
100
0.95
V
CC
+ 25
-25
V
CC
+ 60
V
-60
V
CC
+ 100
-100
+1
7
nA
pF
UNITS
V
nA
V
Note 2:
Limits over temperature are guaranteed by design, not production tested.
Note 3:
Idealized clamp voltages (L1 = L2 = L3 = 0) (Figure 1 ); see the
Applications Information
section for more information.
Note 4:
Guaranteed by design. Not production tested.
2
_______________________________________________________________________________________
Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD
Protection Arrays for High-Speed Data Interfaces
Typical Operating Characteristics
(V
CC
= +5V, T
A
= +25°C, unless otherwise noted.)
CLAMP VOLTAGE vs. DC CURRENT
MAX3202E toc01
MAX3202E/MAX3203E/MAX3204E/MAX3206E
LEAKAGE CURRENT vs. TEMPERATURE
MAX3202E toc02
INPUT CAPACITANCE vs. INPUT VOLTAGE
MAX3202E toc03
1.50
1.30
CLAMP VOLTAGE (V)
1.10
0.90
0.70
0.50
0.30
30
50
70
90
110
130
1000
LEAKAGE CURRENT PER CHANNEL
12
100
INPUT CAPACITANCE (pF)
LEAKAGE CURRENT (pA)
10
8
V
CC
= 3.3V
10
6
V
CC
= 5.0V
4
1
150
25
35
45
55
65
75
85
DC CURRENT (mA)
TEMPERATURE (°C)
2
0
1
2
3
4
5
INPUT VOLTAGE (V)
Pin Description
PIN
MAX3202E
WLP
TDFN-
EP
3, 6
4
1
2, 5
—
MAX3203E
UCSP
A1,
A2, B3
B1
A3
—
—
TDFN-
EP
1, 2, 4
3
6
5
—
MAX3204E
WLP
A1, A2,
B2, B3
B1
A3
—
—
TDFN-
EP
1, 2, 4,
5
3
6
—
—
MAX3206E
WLP
A1, A3,
B1, B3,
C1, C3
A2
C2
—
—
TQFN-
EP
1, 2, 3,
7, 8, 9
5
11
4, 6,
10, 12
—
I/O_
GND
V
CC
N.C.
EP
ESD-Protected Channel
Ground
Power-Supply Input. Bypass V
CC
to
GND with a 0.1μF ceramic capacitor.
No Connection. Not internally
connected.
Exposed Pad. Connect to GND. Only
for TDFN and TQFN package.
NAME
FUNCTION
A1, B2
A2
B1
—
—
_______________________________________________________________________________________
3
Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD
Protection Arrays for High-Speed Data Interfaces
MAX3202E/MAX3203E/MAX3204E/MAX3206E
Detailed Description
The MAX3202E/MAX3203E/MAX3204E/MAX3206E are
diode arrays designed to protect sensitive electronics
against damage resulting from ESD conditions or tran-
sient voltages. The low input capacitance makes these
devices ideal for high-speed data lines. The
MAX3202E, MAX3203E, MAX3204E, and MAX3206E
protect two, three, four, and six channels, respectively.
The MAX3202E/MAX3203E/MAX3204E/MAX3206E are
designed to work in conjunction with a device’s intrinsic
ESD protection. The MAX3202E/MAX3203E/MAX3204E/
MAX3206E limit the excursion of the ESD event to
below ±25V peak voltage when subjected to the
Human Body Model waveform. When subjected to the
IEC 61000-4-2 waveform, the peak voltage is limited to
±60V when subjected to Contact Discharge and ±100V
when subjected to Air-Gap Discharge. The device that
is being protected by the MAX3202E/MAX3203E/
MAX3204E/MAX3206E must be able to withstand these
peak voltages plus any additional voltage generated by
the parasitic board.
d(I
ESD
)
⎞ ⎛
d(I
ESD
)
⎞
⎛
V
C
=
V
CC
+
V
F
(
D1
)
+ ⎜
L1 x
⎟ + ⎜
L2 x
⎠
⎝
dt
⎠ ⎝
dt
⎟
For negative ESD pulses:
⎛
d(I
ESD
)
⎞ ⎛
d(I
ESD
)
⎞ ⎞
⎛
+ ⎜
L3 x
V
C
= − ⎜
V
F
(
D2
)
+ ⎜
L1 x
⎠⎠
⎠
⎝
dt
⎟ ⎝
dt
⎟ ⎟
⎝
where I
ESD
is the ESD current pulse.
POSITIVE SUPPLY RAIL
L2
D1
L1
I/O_
PROTECTED
LINE
D2
Applications Information
Design Considerations
Maximum protection against ESD damage results from
proper board layout (see the
Layout Recommendations
section and Figure 2). A good layout reduces the para-
sitic series inductance on the ground line, supply line,
and protected signal lines.
The MAX3202E/MAX3203E/MAX3204E/MAX3206E ESD
diodes clamp the voltage on the protected lines during
an ESD event and shunt the current to GND or V
CC
. In
an ideal circuit, the clamping voltage, V
C
, is defined as
the forward voltage drop, V
F
, of the protection diode
plus any supply voltage present on the cathode.
For positive ESD pulses:
V
C
= V
CC
+ V
F
For negative ESD pulses:
V
C
= -V
F
In reality, the effect of the parasitic series inductance
on the lines must also be considered (Figure 1).
For positive ESD pulses:
L3
GROUND RAIL
Figure 1. Parasitic Series Inductance
V
CC
L1
PROTECTED LINE
NEGATIVE ESD
CURRENT
PULSE
PATH TO
GROUND
L2
D1
V
C
I/O_
D2
L3
PROTECTED
CIRCUIT
GND
Figure 2. Layout Considerations
4
_______________________________________________________________________________________
Low-Capacitance, 2/3/4/6-Channel, ±15kV ESD
Protection Arrays for High-Speed Data Interfaces
During an ESD event, the current pulse rises from zero
to peak value in nanoseconds (Figure 3). For example,
in a 15kV IEC-61000 Air-Gap Discharge ESD event,
the pulse current rises to approximately 45A in 1ns
(di/dt = 45 x 10
9
). An inductance of only 10nH adds an
additional 450V to the clamp voltage. An inductance of
10nH represents approximately 0.5in of board trace.
Regardless of the device’s specified diode clamp volt-
age, a poor layout with parasitic inductance significantly
increases the effective clamp voltage at the protected
signal line.
A low-ESR 0.1μF capacitor must be used between V
CC
and GND. This bypass capacitor absorbs the charge
transferred by an +8kV IEC-61000 Contact Discharge
ESD event.
Ideally, the supply rail (V
CC
) would absorb the charge
caused by a positive ESD strike without changing its
regulated value. In reality, all power supplies have an
effective output impedance on their positive rails. If a
power supply’s effective output impedance is 1Ω, then
by using V = I
×
R, the clamping voltage of V
C
increas-
es by the equation V
C
= I
ESD
x R
OUT
. An +8kV IEC
61000-4-2 ESD event generates a current spike of 24A,
so the clamping voltage increases by V
C
= 24A
×
1Ω,
or V
C
= 24V. Again, a poor layout without proper
bypassing increases the clamping voltage. A ceramic
chip capacitor mounted as close to the MAX3202E/
MAX3203E/MAX3204E/MAX3206E V
CC
pin is the best
choice for this application. A bypass capacitor should
also be placed as close to the protected device as
possible.
• ±15kV using the Human Body Model
• ±8kV using the Contact Discharge method speci-
fied in IEC 61000-4-2
• ±15kV using the IEC 61000-4-2 Air-Gap Discharge
method
MAX3202E/MAX3203E/MAX3204E/MAX3206E
ESD Test Conditions
ESD performance depends on a number of conditions.
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
Human Body Model
Figure 4 shows the Human Body Model, and Figure 5
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the device through a
1.5kΩ resistor.
R
C
1MΩ
CHARGE-CURRENT-
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
SOURCE
R
D
1.5kΩ
DISCHARGE
RESISTANCE
DEVICE
UNDER
TEST
Cs
100pF
STORAGE
CAPACITOR
±15kV ESD Protection
ESD protection can be tested in various ways; the
MAX3202E/MAX3203E/MAX3204E/MAX3206E are
characterized for protection to the following limits:
Figure 4. Human Body ESD Test Model
I
100%
90%
I
PEAK
I
P
100%
90%
AMPERES
36.8%
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
10%
t
R
= 0.7ns to 1ns
30ns
60ns
t
10%
0
0
t
RL
TIME
t
DL
CURRENT WAVEFORM
Figure 3. IEC 61000-4-2 ESD Generator Current Waveform
Figure 5. Human Body Model Current Waveform
5
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