APRIL 1995
DS3578-2.5
MA2910
MA2910
RADIATION HARD MICROPROGRAM CONTROLLER
The industry standard MA2910 Microprogram Controller
forms part of the MA2900 family of devices.
Offering a building block approach to microcomputer and
controller design, each device in the range is expandable
permitting efficient emulation of any microcode-controlled
machine. The family has been designed for operation in
severe environments such as space, and is qualified to the
highest levels of reliability.
The MA2910 Micro-program Controller is an address
sequencer intended for sequence control of microinstructions
stored in microprogram memory in high speed micro-
processor applications.
All internal elements are full 12 bits wide and address up to
4096 words with one chip. The device has an integral settable
12 bit internal loop counter for repeating instructions and
counting loop iterations.
The MA2910 has four address sources which allow
Microprogram Address to be selected from the microgram
counter, branch address bus, 9 level push/pop stack, or
internal holding register.
The MA2910 supports 100ns cycle times and has an
integral decoder function to enable external devices onto
branch address bus which eliminates the requirement for an
external decoder.
FEATURES
I
Fully Compatible with Industry Standard 2910A
I
CMOS SOS Technology
I
Radiation Hard and High SEU Immunity
I
High Speed / Low Power
I
Fully TTL Compatible
Figure 1: Block Diagram
1
MA2910
OPERATION
The MA2910 is a SOS microprogram controller intended
for use in high speed microprocessor applications. Besides the
capability of sequential access, it provides conditional
branching to any microinstruction within its 4096-microword
range.
A last-in, first-out stack provides microsubroutine return
linkage and looping capability; there are nine nesting levels of
microsubroutines. Microinstruction loop count control is
provided with a count capacity of 4096.
The device is controlled by 16, 4-bit microinstructions. The
PLA decodes the microinstructions on I(3:P) and produces
select control codes for the multiplexer, register/counter,
microprogram counter register, and stack. The 4-bit
microinstructions also generate three active low enable
signals (PL,
VECT,
and
MAP)
for external use. The operation
of each device block is detailed below:
MULTIPLEXER
The MA2910 contains a four-input multiplexer that is used
to select either the register/counter, direct input, microprogram
counter, or stack as the source of the next microinstruction
address.
REGISTER/COUNTER
The register/counter consists of 12 D-type, edgetriggered
flip-flops, with a common clock enable. It is operated during
microinstructions (8,9,15) as a 12-bit down counter, with result
= zero available as a microinstruction branch test criterion.
This provides efficient iteration of microinstructions.
The register/ counter is arranged such that if it is preloaded
with a number N and is then used as a loop termination
counter, the sequence will be executed exactly N+1 times.
During instruction 15, a three way branch under combined
control of the loop counter and the condition code is available.
When its load control, RLD, is LOW, new data is loaded on the
next positive control transition.
The output of the register/counter is available to the
multiplexer as a source for the next microinstruction address.
The direct input furnishes a source of data for loading the
register /counter.
MICROPROGRAM COUNTER-REGISTER
The Microprogram Counter Register (µPC) is composed of
a 12-bit incrementer followed by a 12-bit register. The (µPC)
can be used in one of two ways: When the carry-in to the
incrementer is HIGH, the microprogram register is loaded onto
the next clock cycle with the current Y output word plus one
(Y + 1
¨
µPC). Sequential microinstructions are thus
executed. When the carry-in is LOW, the incrementer passes
the Y output unmodified so that the µPC is reloaded with the
same Y word on the next clock cycle (Y
¨
µPC). The same
microinstruction is thus executed any number of times.
STACK AND STACK POINTER
The third source available at the multiplexer input is a
9-word by 12-bit stack. The stack is used to provide return
address linkage when executing microsubroutines or loops.
The stack contains a built-in stack pointer (SP) which always
points to the last file word written. This allows stack reference
operations (looping) to be performed without a POP.
Explicit control of the stack pointer occurs during
instruction 0 (RESET), which makes the stack empty by
resetting the SP to zero. After a RESET, and whenever the
stack is empty, the contents of the top of the stack are
undefined until a push occurs. Any POPs performed while the
stack is empty put undefined data on the outputs and leave the
stack at zero.
The stack pointer operates as an up/down counter. During
microinstructions 1,4, and 5, the PUSH operation may occur.
This causes the stack pointer to increment and the file to be
written with the required return linkage. On the cycle following
the PUSH, the return data is at the new location pointed to by
the stack pointer.
During five microinstructions, a POP operation may occur.
The stack pointer decrements at the next rising clock edge
following a POP, effectively removing old information from the
top of the stack.
The stack pointer linkage is such that any sequence of
pushes, pops, or stack references can be achieved. At RESET
(instruction 0), the depth of nesting becomes zero. For each
PUSH, the nesting depth increases by one; for each POP, the
depth decreases by one.
PIN DESCRIPTIONS
VDD and GND (Power and Ground)
The MA2910 operates from a single supply voltage of
5V + 10%
D (0 to 11) (Direct input)
These connections provide direct input to the register/
counter, and the multiplexer. D0 is the least significant bit and
D1 the most significant
I (0 to 3) (instruction bus)
The data on these inputs is read on the rising edge of CP. It
determlnes the instruction to be executed in accordance with
table 1.
CC
(Condition Code)
This active low input is used to determine the result of
conditional instructlon. LOW indicates a TRUE conditlon.
CCEN
(Condition code enable)
This active low input enables the CC input. When CCEN is
HIGH, CC is ignored and a conditional operation executed as
though CC were LOW (TRUE).
CI
(Carry input)
When HIGH this input causes the microprogramme
counter register to increment on the rising edge of CP. When
LOW the counter remains unchanged.
RLD
(Register load)
This active low input loads the register/counter from the D
bus on the rising edge of CP. It will override any HOLD or DEC
instruction specified by data on the I bus.
2
MA2910
Y (0 to 11) (Microcode address)
This is a 12 bit wide tristate output bus. It carries the
microcode address generated according to the instruction
read in from the I bus. OE can be used to put the bus in a high
impedance state. This allows another to take control of the
microcode address bus.
OE
(Output enable)
This active low input is used to enable the 12 lines of the Y
bus.
CP (Clock Pulse)
A LOW-to-HlGH transition on this input is used to trigger all
state changes within the device.
FULL
(stack full)
The active low output FULL indicates that 9 items have
been loaded onto the stack .
PL, MAP
&
VECT
(pipeline, map and vector)
These active low outputs are set according to the
instruction being executed. At any time only one is active.
They may be used to select from one of three possible
external sources for microprogramme jumps, being used
directly as three-state enables for these sources.
Typically:
PL
enables the primary source of
microprogramme jumps, usually part of a pipeline register;
MAP
enables a PROM which maps an instruction to a
microcode starting location;
VECT
enables an optional third
source, after a vector from DMA or interrupt source.
I
3
- I
0
MNEMONIC
NAME
FAIL CCEN =
REGISTER LOW & CC =
/CONTROL HIGH
Y
STACK
X
X
X
X
X
X
X
X
≠
0
=0
≠
0
=0
X
X
X
X
X
≠
0
=0
0
PC
D
PC
PC
R
PC
R
F
PC
D
PC
PC
PC
PC
F
PC
F
D
CLEAR
HOLD
HOLD
HOLD
PUSH
PUSH
HOLD
HOLD
HOLD
POP
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
PO P
PASS CCEN =
HIGH & CC =
LOW
Y
STACK
O
D
D
D
PC
D
D
D
F
PC
D
PC
F
D
PC
PC
PC
PC
PC
CLEAR
PUSH
HOLD
HOLD
PUSH
PUSH
HOLD
HOLD
HOLD
POP
HOLD
HOLD
POP
POP
HOLD
POP
HOLD
POP
POP
REGISTER/
CONTROL
ENABLE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
JZ
CJS
JMAP
CJP
PUSH
JSRP
CJV
JRP
RFCT
RPCT
CRTN
CJPP
LDCT
LOOP
CONT
TWB
JUMP ZERO
COND JS P PL
JUMP MAP
COND JUMP PL
PUSH/COND LD
CNTR
COND JSB R/PL
VECTOR
COND JUMP
COND JUMP R/PL
REPEAT LOOP
CNTR
≠
0
REPEAT PL,
CNTR
≠
0
COND RTN
COND JUMP PL
& POP
LD CNTR &
CONTINUE
TEST END LOOP
CONTINUE
THREE-WAY
BRANCH
.
HOLD
HOLD
HOLD
HOLD
Note 1
HOLD
HOLD
HOLD
DEC
HOLD
DEC
HOLD
HOLD
HOLD
LOAD
HOLD
HOLD
DEC
HOLD
PL
PL
MAP
PL
PL
PL
VECT
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
Note 1: If
CCEN
= LOW &
CC
= HIGH, hold, else load.
Figure 2: Table of Instructions
3
MA2910
INSTRUCTION SET
The MA2910 provides 16 instructions which select the
address of the next microinstruction to be executed. 4 of the
instructions are unconditional and their effect depends only on
the instruction. 10 of the instructions have an effect which is
partially controlled by external conditions. 3 of the instructions
have an effect which is partially controlled by the contents of
the internal register/counter. In this discussion it is assumed
the Cl is tied HIGH.
In the 10 conditional instructions, the result of the data-
dependent test is applied to
CC.
If the
CC
input is LOW, the
test is considered passed, and the action specified in the name
occurs; otherwise, the test has failed and an alternate (often
simply the execution of the next sequential microinstruction)
occurs. Testing of
CC
may be disabled for a specific
microinstruction by setting
CCEN
HIGH, which unconditionally
forces the action specified in the name; that is it forces a
pass.Other ways of using
CCEN
include; (1) tying it HIGH,
which is useful if no microinstruction is data-dependent; (2)
tying it LOW if data-dependent instructions are never forced
unconditionally; or (3) tying it to the source of MA2910
instruction bit I
0
, which leaves instructions 4,6 and 10 as data-
dependent but leaves others unconditional. All of these tricks
save one bit of microcode width
The effect of three instructions depend upon the contents
of the register/counter. Unless the counter holds a value of
zero, it is decremented; if it does hold zero, it is held and a
different microprogram next address is selected.These
instructions are useful for executing a microinstruction loop a
finite number of times. Instruction 15 is affected both by the
external condition code and the internal register/counter.
The most effective technique for understanding the
MA2910 is to simply take each instruction and review its
operation. In order to provide some feel for the actual
execution of these instructions, examples of all 16 instructions
are included.
The examples given should be interpreted in the following
manner: The intent is to show microprogram flow as various
microprogram memory words are executed.
For example, the CONTINUE instruction (number 14)
simply means that the contents of the microprogram memory
word 50 are executed, then the contents of word 51 are
executed. This is followed by the contents of 52 and 53 The
microprogram addresses used in the examples were arbitrarily
chosen and have no meaning other than to show instruction
flow. The exception to this is the first example, JUMP ZERO,
which forces the microprogram location counter to address
ZERO. Each dot refers to the time that the contents of the
microprogram memory word is in the pipeline register. While
no special symbology is used for the conditional instructions,
the following text will explain what the conditional choices are
in each example.
Instruction 0: JZ (Jump to Zero, or Reset).
This instruction unconditionally specifies that the address
of the next microinstruction is zero. Many designs use this
feature for power-up sequences and provide the power-up
firmware beginning at microprogram memory word location 0.
Figure 3: 0 JUMP ZERO (JZ)
Instruction 1: Conditional Jump-to-Subroutine.
This instruction is a conditional Jump-to-Subroutine via the
address provided in the pipeline register. As shown in figure 4,
the machine might have executed words at address 50, 51,
and 52. When the contents of address 52 is in the pipeline
register the next address control function is the
CONDITIONAL JUMP-TO-SUBROUTINE. Here, if the test is
passed, the next instruction executed will be the contents of
microprogram memory location 90. If the test has failed, the
JUMP-TO-SUBROUTINE will not be executed; the contents of
microprogram memory location 53 will be executed instead.
Thus, the Conditional Jump-to-Subroutine instruction at
location 52 will cause the instruction either in location 90 or in
location 53 to be executed next. If the test input is such that the
location 90 is selected, value 53 will be pushed onto the
internal stack. This provides the return linkage for the machine
when the subroutine beginning at location 90 is completed. In
this example, the subroutine was completed at location 93 and
a RETURN-FROM-SUBROUTINE would be found at location
93.
Figure 4: COND JSB PL (CJS)
Instruction 2: Jump-Map.
This is an unconditional instruction which causes the
MAP
output to be enabled so that the next microinstruction location
is determined by the address supplied via the mapping
PROMs. Normally, the JUMP MAP instruction is used at the
end of the instruction fetch sequence for the machine.
4
MA2910
Instruction 4: Push/Conditional, Load Counter.
This instruction is used primarily for setting up loops in
microprogram firmware. In this example, when instruction 52 is
in the pipeline register, a PUSH will be made onto the stack
and the counter will be loaded based on the condition. When a
PUSH occurs, the value pushed is always the next sequential
instruction address. In this case, the address is 53. If the test
fails, the counter is not loaded; if it is passed, the counter is
loaded with the value contained in the pipeline register branch
address field.
Thus, a single microinstruction can be used to set up a
loop to be executed a specific number of times. Instruction 8
will describe how to use the pushed value and the register/
counter for looping.
Figure 5: 2 JUMP MAP (JMAP)
In the example of Figure 5, microinstructions at locations
50,51, 52 and 53 might have been the fetch sequence and at
its completion at location 53, the jump map function would be
contained in the pipeline register. This example shows the
mapping PROM outputs to be 90; therefore, an unconditional
jump to microprogram memory address 90 is performed
Instruction 3: Conditional Jump Pipeline.
This instruction derives its branch address from the
pipeline register branch address value (BR
0
-BR
11
). This
instruction provides a technique for branching to various
microprogram sequences depending upon the test condition
inputs. Quite often, state machines are designed which simply
execute tests on various inputs waiting for the condition to
come true. When the true condition is reached, the machine
then branches and executes a set of microinstructions to
perform some functions. This usually has the effect of resetting
the input under test until some point in the future.
The example shows the conditional jump via the pipeline
register address at location 52. When the contents of
mlcroprogram memory word 52 are in the pipeline register, the
next address will be either location 53 or 30, in this example. If
the test is passed, the value currently in the pipeline register
(30) will be selected. If the test fails, the next address selected
will be contained in the microprogram counter which, in this
example, is location 53.
Figure 7: 4 PUSH/COND LD CNTR (PUSH)
Instruction 5: Conditional Jump-to-Subroutine.
This instruction is a Conditional Jump-to-Subroutine via the
register/counter of the contents of the PIPELINE register. A
PUSH is always performed and one of two subroutines
executed. In this example, either the subroutine beginning at
address 80 or the subroutine beginning at address 90 will be
performed. A RETURN-FROM-SUBROUTINE (instruction
number 10) returns the microprogram flow to address 55.
In order for this microinstruction control sequence to
operate correctly, both the next address fields of instruction 53
and the next address fields of instruction 54 would have to
contain the proper value. Lets assume that the branch address
Figure 6: 3 COND JUMP PL (CLP)
Figure 8: 5 COND JSB R/PL (JSRP)
5
FPGA/CPLD
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