ADVANCE INFORMATION
3797-2·2
MA818
THREE-PHASE PULSE WIDTH MODULATION WAVEFORM GENERATOR
The MA818 PWM generator has been designed to provide
waveforms for the control of variable speed AC machines,
uninterruptible power supplies and other forms of power elec-
tronic devices which require pulse width modulation as a means
of efficient power control.
The six TTL level PWM outputs (Fig. 2) control the six
switches in a three-phase inverter bridge. This is usually via an
external isolation and amplification stage.
Rotational frequency is defined to 12 bits for high accuracy
and a zero setting is included in order to implement DC injection
braking with no software overhead. Any power waveform can be
implemented as this is user-defined in an external PROM/
EPROM. For users requiring an on-chip pre-programmed wave-
form, the functionally identical MA828 is recommended.
Information contained within the pulse width modulated
sequences controls the shape, power frequency, amplitude, and
rotational direction (as defined by the red-yellow-blue phase
sequence) of the output waveform. Parameters such as the
carrier frequency, minimum pulse width, and pulse delay time
may be defined during the initialisation of the device. The pulse
delay time (underlap) controls the delay between turning on and
off the two power switches in each output phase of the inverter
bridge, in order to accommodate variations in the turn-on and
turn-off times of families of power devices.
The MA818 is easily controlled by a microprocessor and its
fully-digital generation of PWM waveforms gives unprecedented
accuracy and temperature stability. Precision pulse shaping
capability allows optimum efficiency with any power circuitry.
The device operates as a stand-alone microprocessor periph-
eral, reading the power waveform directly from a PROM/EPROM
and requiring microprocessor intervention only when operating
parameters need to be changed.
An 8-bit multiplexed data bus is used to receive addresses and
data from the microprocessor/controller. This is a standard MOTEL
TM
bus, compatible with most microprocessors/controllers.
The MA818 is fabricated in CMOS for low power consumption.
AD
0
AD
1
AD
2
AD
3
AD
4
AD
5
AD
6
AD
7
WR* (R/W†)
RD* (DS†)
ALE* (AS†)
RST
CLK
CS
TRIP
ZPP
RPHB
YPHB
BPHB
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
V
DD
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
D
1
D
2
D
3
SET TRIP
RPHT
YPHT
BPHT
MA818
31
30
29
28
27
26
25
24
23
22
21
DC40
DG40
DP40
*
= Intel bus format
† = Motorola bus format
AD
4
AD
3
AD
2
AD
1
AD
0
V
DD
A
10
NC
A
9
A
8
A
7
39
38
37
36
35
6
5
4
3
2
1
44 43 42 41 40
AD
5
AD
6
AD
7
WR* (R/W†)
7
8
9
10
11
12
13
14
15
16
A
6
A
5
A
4
A
3
A
2
NC
A
1
A
0
D
0
D
1
D
2
FEATURES
s
Fully Digital Operation
RD* (DS†)
NC
ALE* (AS†)
RST
CLK
CS
TRIP
MA818
34
33
32
31
30
s
Interfaces with Most Microprocessors
s
Wide Power-Frequency Range
s
Carrier Frequency Selectable up to 24kHz
s
Waveform Stored in External PROM/EPROM
s
Double Edged Regular Sampling
s
Selectable Minimum Pulse Width and Underlap Time
s
DC Injection Braking
MOTEL is a registered Trademark of Intel Corp. and Motorola Corp.
17
29
18 19 20 21 22 23 24 25 26 27 28
RPHB
YPHB
BPHB
ZPP
BPHT
YPHT
RPHT
NC
SET TRIP
V
SS
D
3
HP44
Fig. 1 Pin connections – top view (not to scale)
MA818
PIN DESCRIPTIONS
Pin.no.
DC/DG/DP40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin.no.
HP44
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
Name
AD
0
AD
1
AD
2
AD
3
AD
4
AD
5
AD
6
AD
7
Intel: WR
Motorola: R/W
Intel: RD
Motorola: DS
Intel: ALE
Motorola: AS
RST
CLK
CS
TRIP
ZPP
RPHB
YPHB
BPHB
V
SS
BPHT
YPHT
RPHT
SET TRIP
D
3
D
2
D
1
D
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
V
DD
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
P
O
O
O
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
P
Function
Multiplexed Address/Data (LSB)
Multiplexed Address/Data
Multiplexed Address/Data
Multiplexed Address/Data
Multiplexed Address/Data
Multiplexed Address/Data
Multiplexed Address/Data
Multiplexed Address/Data(MSB)
Intel bus control: Write Strobe
Motorola bus control: Read/Write select
Intel bus control: Read Strobe
Motorola bus control: Data Strobe
Intel bus control: Address Latch Enable
Motorola bus control: Address Strobe
Reset internal counters, active low
Clock input
Chip Select input, active low
Output trip status; low = output tripped
Zero Phase Pulse
Red Phase, Bottom power switch
Yellow Phase, Bottom power switch
Blue Phase, Bottom power switch
Negative power supply (0V)
Blue Phase, Top power switch
Yellow Phase, Top power switch
Red Phase, Top power switch
Set output trip. 90kΩ internal pull-up resistor
Eprom Data (LSB)
Eprom Data
Eprom Data
Eprom Data (MSB)
Eprom Address (LSB)
Eprom Address
Eprom Address
Eprom Address
Eprom Address
Eprom Address
Eprom Address
Eprom Address
Eprom Address
Eprom Address
Eprom Address (LSB)
Positive power supply
2
MA818
RST
CS
MOTEL
INTERFACE
8
BUS
CONTROL
RED PHASE
PULSE
DELETION
PULSE
DELAY
CIRCUIT
RPHT
RPHB
SYSTEM
BUS
AD
0
-AD
7
BUS
DEMULTIPLEXER
R0
R1
R2
R3
R4
24-BIT
INITIALISATION
REGISTER
PHASING
AND
CONTROL
LOGIC
YELLOW PHASE
PULSE
DELETION
PULSE
DELAY
CIRCUIT
YPHT
YPHB
24-BIT
CONTROL
REGISTER
BLUE PHASE
PULSE
DELETION
PULSE
DELAY
CIRCUIT
BPHT
BPHB
CLOCK
CLOCK
DIVIDER
ADDRESS
DATA
GENERATOR BUFFER
11
4
TRIP
LATCH
TRIP
A
0
-A
10
D
0
-D
3
TO
FROM
WAVEFORM STORAGE
PROM/EPROM
SET
TRIP
Fig. 2 MA818 internal block diagram
FUNCTIONAL DESCRIPTION
An asynchronous method of PWM generation is used with
uniform or ‘double-edged’ regular sampling of the waveform
stored in the PROM/EPROM as illustrated in Fig.3. The use of
an external PROM/EPROM allows the user to define the opti-
mum power waveform for the particular motor being used.
The triangle carrier wave frequency is selectable up to 24kHz
(assuming the maximum clock frequency of 12.5MHz is used)
enabling ultrasonic operation for noise critical applications.
Power frequency ranges of up to 4kHz (with 12.5MHz clock) are
possible, with the actual output frequency resolved to 12-bit
accuracy within the chosen range in order to give precise motor
speed control and smooth frequency changing. The output
phase sequence of the PWM outputs can also be changed to
allow both forward and reverse motor operation.
PWM output pulses can be ‘tailored’ to the inverter character-
istics by defining the minimum allowable pulse width (the MA818
will delete all shorter pulses from the ‘pure’ PWM pulse train) and
the pulse delay (underlap) time without the need for external
circuitry. This gives cost advantages in both component savings
and in allowing the same PWM circuitry to be used for control of
a number of different motor drive circuits simply by changing the
microprocessor software.
Power frequency amplitude control is also provided with an
overmodulation option to assist in rapid motor braking.
An asynchronous trip input allows the PWM outputs to be
shut down immediately, overriding the microprocessor control in
the event of an emergency.
Other possible MA818 applications are as a 3-phase wave-
form generator as part of a switched-mode power supply (SMPS)
or of an uninterruptible power supply (UPS). In such applications
the high carrier frequency allows a very small switching trans-
former to be used.
MICROPROCESSOR INTERFACE
The MA818 interfaces to the controlling microprocessor by
means of a multiplexed bus of the MOTEL format. This interface
bus has the ability to adapt itself automatically to the format and
timing of both MOTorola and IntEL interface buses (hence
MOTEL). Internally, the detection circuitry latches the status of
the DS/RD line when AS/ALE goes high. If the result is high.
Then the Intel mode is used; if the result is low then the Motorola
mode is used. This procedure is carried out each time that AS/
ALE goes high. In practice this mode selection is transparent to
the user. For bus connection and timing information refer to the
description relevant to the microprocessor/controller being used.
Industry standard microprocessors such as the 8085, 8088,
etc. and microcontrollers such as the 8051, 8052 and 6805 are
all compatible with the interface on the MA818. This interface
consists of 8 data lines, AD
0
- AD
7
(write only in this instance),
which are multiplexed to carry both the address and data
information, 3 bus control lines, labelled WR,RD and ALE in Intel
mode and R/W, DS and AS in Motorola mode, and a Chip Select
input. CS, which allows the MA818 to share the same bus as
other microprocessor peripherals. It should be noted that all bus
timings are derived from the microprocessor and are independ-
ent of the MA818 clock input.
3
MA818
TRIANGLE WAVE AT
CARRIER FREQUENCY,
SAMPLING ON
1VE
AND
2VE
PEAKS
PWM SWITCHING
INSTANTS
11
0
POWER WAVEFORM
AS READ FROM
EXTERNAL
PROM/EPROM
21
11
RESULTING
PWM
WAVEFORM
0
21
Fig. 3 Asynchronous PWM generation with‘double-edged’ regular sampling as used by the MA818
t
1
ALE
AS
t
1
t
2
RD
t
4
t
3
t
5
t
7
t
2
WR
t
3
t
4
DS
t
6
t
8
t
9
R/W
CS
t
8
t
10
t
11
CS
t
9
AD
0
-AD
7
t
10
t
11
t
15
LATCH ADDRESS
t
12
LATCH DATA
AD
0
-AD
7
t
15
LATCH ADDRESS
t
12
LATCH DATA
Fig. 4 Intel bus timing definitions
Parameter
ALE high period
Delay time, ALE to WR
WR low period
Delay time, WR high to ALE high
CS setup time
CS hold time
Address setup time
Address hold time
Data setup time
Data hold time
Symbol
t
1
t
2
t
3
t
4
t
8
t
9
t
10
t
15
t
11
t
12
Min.
70
40
200
40
20
0
30
30
100
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fig. 5 Motorola bus timing definitions
Parameter
AS high period
Delay time, as low to DS high
DS high period
Delay time, DS low to AS high
DS low period
DS high to R/W low setup time
R/W hold time
CS setup time
CS hold time
Address setup time
Address hold time
Write data setup time
Write data hold time
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
15
t
11
t
12
Min.
90
40
210
40
200
10
10
20
0
30
30
110
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 1 Intel bus timings at V
DD
= 5V, T
AMB
=
1
25°C
Table 2 Motorola bus timings at V
DD
= 5V, T
AMB
=
1
25°C
4
MA818
MICROPROCESSOR BUS TIMING
Intel Mode (Fig. 4 and Table 1)
The address is latched by the falling edge of ALE. Data is
written from the bus into the MA818 on the rising edge of WR. RD
is not used in this mode because the registers in the MA818 are
write only. However, this pin must be connected to RD (or tied
high) to enable the MA818 to select the correct interface format.
Power frequency range
This sets the maximum power frequency that can be carried
within the PWM output waveforms. This would normally be set
to a value to prevent the motor system being operated outside
its design parameters.
Pulse delay time ('underlap')
For each phase of the PWM cycle there are two control
signals, one for the top switch connected to the positive inverter
DC supply and one for the bottom switch connected to the
negative inverter DC supply. In theory, the states of these two
switches are always complementary. However, due to the finite
and non-equal turn-on and turn- off times of power devices, it is
desirable when changing the state of the output pair, to provide
a short delay time during which both outputs are off in order to
avoid a short circuit through the switching elements.
Pulse deletion time
A pure PWM sequence produces pulses which can vary in
width between 0% and 100% of the duty cycle. Therefore, in
theory, pulse widths can become infinitesimally narrow. In
practice this causes problems in the power switches due to
storage effects and therefore a minimum pulse width time is
required. All pulses shorter than the minimum specified are
deleted.
Counter reset
This facility allows the internal power frequency counter of the
MA818 to be set to zero, disabling the normal frequency control
and giving a 50% output duty cycle.
Motorola Mode (Fig. 5 and Table 2)
The address is latched on the falling edge of the AS line. Data
is written from the bus into the MA818 (only when R/W is low) on
the falling edge of DS (providing CS is low).
CONTROLLLNG THE MA818
The MA818 is controlled by loading data into two 24-bit
registers via the microprocessor interface. These registers are
the initialisation register and the control register.
The initialisation register would normally be loaded before
motor operation (i.e., prior to the PWM outputs being activated)
and sets up the basic operating parameters associated with the
motor and inverter. This data would not normally be updated
during motor operation.
The control register is used to control the PWM outputs (and
hence the motor) during operation e.g., stop/start, speed, for-
ward/reverse etc. and would normally be loaded and changed
only after the initialisation register has been loaded.
As the MOTEL bus interface is restricted to an 8-bit wide
format, data to be loaded into either of the 24-bit register is first
written to three 8-bit temporary registers R0, R1 and R2 before
being transferred to the desired 24-bit register. The data is
accepted (and acted upon) only when transferred to one of the
24-bit registers.
Transfer of data from the temporary registers to either the
initialisation register or the control register is achieved by a write
instruction to a dummy register. Writing to dummy register R3
results in data transfer from R0, R1 and R2 to the control register,
while writing to dummy register R4 transfers data from R0, R1
and R2 to the initialisation register. It does not matter what data
is written to the dummy registers R3 and R4 as they are not real
registers. It is merely the write instruction to either of these
registers which is acted upon in order to load the initialisation and
control registers.
AD
2
0
0
0
0
1
AD
1
0
0
1
1
0
AD
0
0
0
0
0
1
Register
R0
R1
R2
R3
R4
Comment
Temporary register R0
Temporary register R1
Temporary register R2
Transfers control data
Transfers initialisation data
Initialisation Register Programming
The initialisation register data is loaded in 8-bit segments into the
three 8-bit temporary registers R0-R2. When all the initialisation data
has been loaded into these registers it is transferred into the 24-bit
initialisation register by writing to the dummy register R4.
FRS
2
FRS
1
FRS
0
X
X
CFS
2
CFS
2
CFS
2
FREQUENCY
RANGE
SELECT WORD
FRS
2
=
MSB
FRS
0
=
LSB
DON’T
CARE
Fig. 6 Temporary register R1
Carrier frequency selection
The carrier frequency is a function of the externally applied
clock frequency and a division ratio
n,
determined by the 3-bit
CFS word set during initialisation. The values of
n
are selected
as shown in Table 4.
CFS word
Value of n
101
32
100
16
011
8
010
4
001
2
000
1
Table 3 MA818 register addressing
Initialisation Register Function
The 24-bit initialisation register contains parameters which,
under normal operation, will be defined during the power-up
sequence. These parameters are particular to the drive circuitry
used, and therefore changing these parameters during a PWM
cycle is not recommended. Information in this register should
only be modified while RST is active (i.e. low) so that the PWM
outputs are inhibited (low) during the updating process.
The parameters set in the initialisation register are as follows:
Carrier frequency
Low carrier frequencies reduce switching losses whereas
high carrier frequencies increase waveform resolution and can
allow ultrasonic operation.
Table 4 Values of clock division ratio n
The carrier frequency,
f
CARR
,
is then given by:
f
CARR
=
k
5123n
where
k
= clock frequency and
n
= 1, 2, 4, 8, 16 or 32 (as set by
CFS)
Power frequency range selection
The power frequency range selected here defines the maximum
limit of the power frequency. The operating power frequency is
controlled by the 12-bit Power Frequency Select (PFS) word in the
control register but may not exceed the value set here.
CARRIER
FREQUENCY
SELECT WORD
CFS
2
=
MSB
CFS
0
=
LSB
5
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