UVLO, SYNC Voltage...................................–0.3V to V
CC
FB Current ..............................................................±2mA
V
CMP
Current .........................................................±1mA
Operating Ambient Temperature Range (Notes 4, 5)
LTC4268-1C ............................................. 0°C to 70°C
LTC4268-1I .......................................... –40°C to 85°C
Junction Temperature (Note 5) ............................. 150°C
Storage Temperature Range................... –65°C to 150°C
V
CC
10
t
ON
11
ENDLY 12
SYNC 13
SFST 14
OSC 15
FB 16
DKD32 PACKAGE
32-LEAD (7mm × 4mm) PLASTIC DFN
T
JMAX
= 150°C,θ
JA
= 49°C/W,
θ
JC
= 4.7°C/W
EXPOSED PAD (PIN 33) MUST BE SOLDERED TO
HEATSINKING PLANE THAT IS ELECTRICALLY CONNECTED TO GND
ORDER INFORMATION
LEAD FREE FINISH
LTC4268CDKD-1#PBF
LTC4268IDKD-1#PBF
LEAD BASED FINISH
LTC4268CDKD-1
LTC4268IDKD-1
TAPE AND REEL
LTC4268CDKD-1#TRPBF
LTC4268IDKD-1#TRPBF
TAPE AND REEL
LTC4268CDKD-1#TR
LTC4268IDKD-1#TR
PART MARKING*
42681
42681
PART MARKING*
42681
42681
PACKAGE DESCRIPTION
32-Lead (7mm
×
4mm) Plastic DFN
32-Lead (7mm
×
4mm) Plastic DFN
PACKAGE DESCRIPTION
32-Lead (7mm
×
4mm) Plastic DFN
32-Lead (7mm
×
4mm) Plastic DFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
42681fa
2
LTC4268-1
ELECTRICAL CHARACTERISTICS
SYMBOL
V
PORT
PARAMETER
Supply Voltage
IEEE 802.3af System
Signature Range
Classification Range
UVLO Turn-On Voltage
UVLO Turn-Off Voltage
V
TURNON
V
TURNOFF
V
HYST
V
CLAMP
I
VCC
I
VCC_START
V
FB
I
FB_BIAS
g
m
I
FB
V
FBCLAMP
%V
REF
A
V
I
SFST
I
SFST
V
CMP_THLD
V
PG_HIGH
,
V
SG_HIGH
V
PG_LOW
,
V
SG_LOW
V
PG_SHDN
,
V
SG_SHDN
t
PG_RISE
,
t
SG_RISE
t
PG_FALL
,
t
SG_FALL
V
SENSE_LIM
ΔV
SENSE
/ΔV
CMP
V
SENSE_OC
V
IH_SHDN
V
IL_SHDN
PG, SG, Output Shutdown Strength
PG, SG Rise Time
PG, SG Fall Time
Switch Current Threshold at Maximum
V
CMP
Sense Threshold vs V
CMP
Sense Pin Overcurrent Fault Voltage
Shutdown High Level Input Voltage
Shutdown Low Level Input Voltage
V
SENSE+
, V
SFST
< 1V
With Respect to V
PORTN
High Level = Shutdown (Note 12)
With Respect to V
PORTN
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 14V, SG open, V
CMP
= 1.5V, V
SENSE
= 0V, R
CMP
= 1k, R
tON
= 90k,
R
PGDLY
= 27.4k, R
ENDLY
= 90k, unless otherwise specified.
CONDITIONS
Voltage with Respect to V
PORTP
Pin
(Notes 6, 7, 8, 9, 10)
MIN
TYP
MAX
UNITS
l
l
l
l
l
l
l
l
l
l
l
l
–1.5
–12.5
–37.7
–29.8
14
8
4
19.5
4
1.22
700
25
–38.9
–30.6
15.3
9.7
5.6
20.2
6.4
180
1.237
200
1000
55
2.56
0.84
–57
–10.1
–21
–40.2
–31.5
16.6
11
7.2
V
V
V
V
V
V
V
V
V
V
CC
Turn-On Voltage
V
CC
Turn-Off Voltage
V
CC
Hysteresis
V
CC
Shunt Regulator Voltage
V
CC
Supply Current
V
CC
Start-Up Current
Feedback Regulation Voltage
Feedback Pin Input Bias Current
Feedback Amplifier
Transconductance
Feedback Amplifier Source or Sink
Current
Feedback Amplifier Clamp Voltage
Reference Voltage Line Regulation
Feedback Amplifier Voltage Gain
Soft-Start Charging Current
Soft-Start Discharge Current
Control Pin Threshold (VCMP)
PG, SG, Output High Level
PG, SG, Output Low Level
Voltage with Respect to GND
Voltage with Respect to GND
V
TURNON
– V
TURNOFF
I
VCC
= 15mA, V
UVLO
= 0V, Voltage with
Respect to GND
V
CMP
= Open (Note 11)
V
CC
= 10V
R
CMP
Open
10
400
1.251
1400
90
mA
μA
V
nA
A/V
μA
V
V
l
l
V
FB
= 0.9V
V
FB
= 1.4V
12V ≤ V
CC
≤ 18V
V
CMP
= 1.2V to 1.7V
V
SFST
= 1.5V
V
SFST
= 1.5V, V
UVLO
= 0V
Duty Cycle = Min
l
l
l
0.005
1500
16
0.8
6.6
20
1.3
1
7.4
0.01
1.4
15
15
0.02
25
%/V
V/V
μA
mA
V
8
0.05
2.3
V
V
V
ns
ns
V
UVLO
= 0V; I
PG
, I
SG
= 20mA
C
PG
, C
SG
= 1nF
C
PG
, C
SG
= 1nF
Measured at V
SENSE+
l
l
88
100
0.07
205
110
mV
V/V
230
57
0.45
mV
V
V
3
42681fa
3
LTC4268-1
ELECTRICAL CHARACTERISTICS
SYMBOL
R
INPUT_SHDN
V
IH_ILIM
V
IL_ILIM
I
VPORTN
I
IN_CLASS
ΔI
CLASS
R
SIGNATURE
PARAMETER
Shutdown Input Resistance
I
LIM_EN
High Level Input Voltage
I
LIM_EN
Low Level Input Voltage
V
PORTN
Supply Current
IC Supply Current During Classification
Current Accuracy During Classification
Signature Resistance
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 14V, SG open, V
CMP
= 1.5V, V
SENSE
= 0V, R
CMP
= 1k, R
tON
= 90k,
R
PGDLY
= 27.4k, R
ENDLY
= 90k, unless otherwise specified.
CONDITIONS
With Respect to V
PORTN
With Respect to V
PORTN
(Note 13)
High Level Enables Current Limit
With Respect to V
PORTN
(Note 13)
V
PORTN
= –54V
V
PORTN
= –17.5V, V
NEG
Tied to V
PORTP
(Note 14)
10mA < I
CLASS
< 75mA
–12.5V ≤ V
PORTN
≤ –21V (Notes 15, 16)
–1.5V ≤ V
PORTN
≤ –10.1V, SHDN Tied
to V
PORTN
, IEEE 802.3af Two-Point
Measurement (Notes 8, 9)
–1.5V ≤ V
PORTN
≤ –10.1V, SHDN Tied
to V
PORTP
, IEEE 802.3af Two-Point
Measurement (Notes 8, 9)
I = 1mA, V
PORTN
= –54V,
PWRGD
Referenced to V
PORTN
I = 0.5mA, V
PORTN
= –52V, V
NEG
= –4V
PWRGD Referenced to V
NEG
(Note 17)
I = 2mA, V
NEG
= 0V, PWRGD Referenced to
V
NEG
(Note 3)
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
MIN
100
4
TYP
MAX
UNITS
kΩ
V
1
3
0.55
0.62
0.70
±3.5
23.25
26
V
mA
mA
%
kΩ
R
INVALID
Invalid Signature Resistance
10
11.8
kΩ
V
PWRGD_OUT
I
PWRGD_LEAK
V
PWRGD_OUT
V
PWRGD_VCLAMP
I
PWRGD_LEAK
R
ON
I
OUT_LEAK
I
LIM_HI
I
LIM_LO
I
LIM_DISA
Active Low Power Good Output Voltage
0.5
1
0.35
12
14
16.5
1
0.5
0.6
0.8
1
700
250
1.2
750
300
1.45
800
350
1.65
V
μA
V
V
μA
Ω
Ω
μA
mA
mA
A
Active Low Power Good Output Leakage V
PORT
= 0V, V
PWRGD
= 57V
Active High Power Good Output Voltage
Active High Power Good Voltage
Limiting Clamp
Active High Power Good Output Leakage V
PWRGD
= 11V with Respect to V
NEG
,
V
NEG
= V
PORTN
= –54V
On-Resistance
V
OUT
Leakage
Input Current Limit, High Level
Input Current Limit, Low Level
Safeguard Current Limit When I
LIM
is
Disabled
Oscillator Frequency
Oscillator Capacitor Value
Minimum Switch on Time
Flyback Enable Delay Time
PG Turn-On Delay Time
Maximum Switch Duty Cycle
SYNC Pin Threshold
SYNC Pin Input Resistance
I = 700mA, V
PORTN
= –48V, Measured from
V
PORTN
to V
NEG
(Note 16)
V
PORTN
= –57V, V
PORTP
= SHDN = V
NEG
=
0V (Note 15)
V
PORTN
= –54V, V
NEG
= –53V I
LIM_EN
Floating (Notes 18, 19)
V
PORTN
= –54V, V
NEG
= –53V
(Notes 18, 19)
V
PORTN
= –54V,
V
NEG
= –52.5V I
LIM_EN
Tied To V
PORTN
(Notes 18, 19, 20)
C
OSC
= 100pF
(Note 21)
f
OSC
C
OSC
t
ON(MIN)
t
ENDLY
t
PGDLY
DC
ON(MAX)
V
SYNC
R
SYNC
l
84
33
100
200
265
200
110
200
kHz
pF
ns
ns
ns
%
l
l
85
88
1.53
40
2.1
V
kΩ
42681fa
4
LTC4268-1
ELECTRICAL CHARACTERISTICS
SYMBOL
I
LCOMP
V
LCOMP
V
UVLO
I
UVLOL
I
UVLOH
PARAMETER
Feedback Pin Load Compensation
Current
Load Comp to V
SENSE
Offset Voltage
UVLO Pin Threshold
UVLO Pin Bias Current
V
UVLO
= 1.2V
V
UVLO
= 1.3V
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 14V, SG open, V
CMP
= 1.5V, V
SENSE
= 0V, R
CMP
= 1k, R
tON
= 90k,
R
PGDLY
= 27.4k, R
ENDLY
= 90k, unless otherwise specified.
CONDITIONS
V
RCMP
with V
SENSE+
= 0V
V
SENSE+
= 20mV, V
FB
= 1.23V
l
MIN
TYP
20
1
MAX
UNITS
μA
mV
1.215
–0.25
–4.50
1.237
0
–3.4
1.265
0.25
–2.5
V
μA
μA
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All voltages are with respect to V
PORTP
pin unless otherwise noted.
Note 3:
Active High PWRGD internal clamp circuit self-regulates to 14V
with respect to V
NEG
. V
CC
has internal 20V clamp with respect to GND.
Note 4:
This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5:
T
J
is calculated from the ambient temperature T
A
and power
dissipation P
DIS
according to the formula:
T
J
= T
A
+ (P
DIS
• 49°C/W)
Note 6:
The LTC4268-1 operates with a negative supply voltage in the
range of –1.5V to –57V. To avoid confusion, voltages in this data sheet
are referred to in terms of absolute magnitude. Terms such as “maximum
negative voltage” refer to the largest negative voltage and a “rising
negative voltage” refers to a voltage that is becoming more negative.
Note 7:
In IEEE 802.3af systems, the maximum voltage at the PD jack is
defined to be –57V.
Note 8:
The LTC4268-1 is designed to work with two polarity protection
diodes in series with the input. Parameter ranges specified in the Electrical
Characteristics are with respect to LTC4268-1 pins and are designed to
meet IEEE 802.3af specifications when the drop from the two diodes is
included. See Applications Information.
Note 9:
Signature resistance is measured via the two-point
ΔV/ΔI
method
as defined by IEEE 802.3af. The LTC4268-1 signature resistance is offset
from 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af
specifications. The minimum probe voltages measured at the LTC4268-1
pins are –1.5V and –2.5V. The maximum probe voltages are –9.1V and
–10.1V.
Note 10:
The LTC4268-1 includes hysteresis in the UVLO voltages to
preclude any start-up oscillation. Per IEEE 802.3af requirements, the
LTC4268-1 will power up from a voltage source with 20Ω series resistance
on the first trial.
Note 11:
Supply current does not include gate charge current to the
MOSFETs. See Application Information.
Note 12:
To disable the 25k signature, tie SHDN to V
PORTP
(±0.1V) or hold
SHDN high with respect to V
IN
. See Applications Information.
Note13:
I
LIM_EN
pin is pulled high internally and for normal operation
should be left floating. To disable current limit, tie I
LIM_EN
to V
IN
. See
Applications Information.
Note 14:
I
IN_CLASS
does not include classification current programmed at
Pin 3. Total supply current in classification mode will be I
IN_CLASS
+ I
CLASS
(See Note 15).
Note 15:
I
CLASS
is the measured current flowing through R
CLASS
.
ΔI
CLASS
accuracy is with respect to the ideal current defined as I
CLASS
= 1.237/
R
CLASS
. T
CLASSRDY
is the time for I
CLASS
to settle to within ±3.5% of ideal.
The current accuracy specification does not include variations in R
CLASS
resistance. The total classification current for a PD also includes the IC
quiescent current (I
IN_CLASS
). See Applications Information.
Note 16:
This parameter is assured by design and wafer level testing.
Note 17:
Active high power good is referenced to V
NEG
and is valid for
V
PORTP
– V
NEG
≥ 4V.
Note 18:
The LTC4268-1 includes a dual current limit. At turn on, before
C1 is charged, the LTC4268-1 current level is set to I
LIMIT_LOW
. After C1 is
charged and with I
LIM_EN
floating, the LTC4268-1 switches to I
LIMIT_HIGH
.
With I
LIM_EN
pin tied low, the LTC4268-1 switches to I
LIMIT_DISA
. The
LTC4268-1 stays in I
LIMIT_HIGH
or I
LIMIT_DISA
until the input voltage drops
below the UVLO turn-off threshold or a thermal overload occurs.
Note 19:
The LTC4268-1 features thermal overload protection. In the event
of an over temperature condition, the LTC4268-1 will turn off the power
MOSFET, disable the classification load current, and present an invalid
power good signal. Once the LTC4268-1 cools below the over temperature
limit, the LTC4268-1 current limit switches to I
LIMIT_LOW
and normal
operation resumes.
Note 20:
I
LIMIT_DISA
is a safeguard current limit that is activated when the
normal input current limit (I
LIMIT_HIGH
) is defeated using the I
LIM_EN
pin.
Currents at or near I
LIMIT_DISA
will cause significant package heating and
may require a reduced maximum ambient operating temperature in order
to avoid tripping the thermal overload protection.
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