电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

LTC2273CUJ

产品描述16-Bit, 80Msps/65Msps Serial Output ADC
产品类别模拟混合信号IC    转换器   
文件大小765KB,共44页
制造商Linear ( ADI )
官网地址http://www.analog.com/cn/index.html
下载文档 详细参数 全文预览

LTC2273CUJ概述

16-Bit, 80Msps/65Msps Serial Output ADC

LTC2273CUJ规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称Linear ( ADI )
零件包装代码QFN
包装说明HVQCCN, LCC40,.24SQ,20
针数40
Reach Compliance Code_compli
ECCN代码3A001.A.5.A.5
最大模拟输入电压1.5 V
最小模拟输入电压1 V
转换器类型ADC, PROPRIETARY METHOD
JESD-30 代码S-PQCC-N40
JESD-609代码e0
长度6 mm
最大线性误差 (EL)0.0069%
湿度敏感等级1
模拟输入通道数量1
位数16
功能数量1
端子数量40
最高工作温度70 °C
最低工作温度
输出位码OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式SERIAL
封装主体材料PLASTIC/EPOXY
封装代码HVQCCN
封装等效代码LCC40,.24SQ,20
封装形状SQUARE
封装形式CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度)235
电源3.3 V
认证状态Not Qualified
采样速率80 MHz
采样并保持/跟踪并保持SAMPLE
座面最大高度0.8 mm
标称供电电压3.3 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式NO LEAD
端子节距0.5 mm
端子位置QUAD
处于峰值回流温度下的最长时间20
宽度6 mm
Base Number Matches1

文档预览

下载PDF文档
FEATURES
n
n
n
n
n
n
n
n
n
n
n
n
LTC2273/LTC2272
16-Bit, 80Msps/65Msps
Serial Output ADC
DESCRIPTION
The LTC
®
2273/LTC2272 are 80Msps/65Msps, 16-bit A/D
converters with a high speed serial interface. They are
designed for digitizing high frequency, wide dynamic
range signals with an input bandwidth of 700MHz. The
input range of the ADC can be optimized using the PGA
front end. The output data is serialized according to the
JEDEC serial interface for data converters specification
(JESD204).
The LTC2273/LTC2272 are perfect for demanding applica-
tions where it is desirable to isolate the sensitive analog
circuits from the noisy digital logic. The AC performance
includes a 77.7dB Noise Floor and 100dB spurious free
dynamic range (SFDR). Ultra low internal jitter of 80fs
RMS allows undersampling of high input frequencies
with excellent noise performance. Maximum DC specs
include ±4.5LSB INL and ±1LSB DNL (no missing codes)
over temperature.
The encode clock inputs, ENC
+
and ENC
, may be driven
differentially or single-ended with a sine wave, PECL,
LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer
allows high performance at full speed with a wide range
of clock duty cycles.
L,
LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
n
High Speed Serial Interface (JESD204)
Sample Rate: 80Msps/65Msps
77.7dBFS Noise Floor
100dB SFDR
SFDR >90dB at 140MHz (1.5V
P-P
Input Range)
PGA Front End (2.25V
P-P
or 1.5V
P-P
Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Single 3.3V Supply
Power Dissipation: 1100mW/990mW
Clock Duty Cycle Stabilizer
Pin Compatible Family
105Msps: LTC2274
80Msps: LTC2273
65Msps: LTC2272
40-Pin 6mm
×
6mm QFN Package
APPLICATIONS
n
n
n
n
n
n
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
TYPICAL APPLICATION
3.3V
SENSE
V
CM
1.25V
COMMON MODE
BIAS VOLTAGE
INTERNAL ADC
REFERENCE
GENERATOR
FAM
SYNC
+
8B/10B
ENCODER
16
20
SYNC
OV
DD
1.2V TO 3.3V
0.1μF
50Ω
A
IN +
ANALOG
INPUT
A
IN
ASIC OR FPGA
128k Point FFT, f
IN
= 4.93MHz,
–1dBFS, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
2.2μF
50Ω
AMPLITUDE (dBFS)
CMLOUT
+
+
SERIAL
RECEIVER
+
S/H
AMP
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
ENC
+
ENC
16-BIT
PIPELINED
ADC CORE
SERIALIZER
CORRECTION
LOGIC
CMLOUT
SCRAMBLER/
PATTERN
GENERATOR
PGA DITH MSBINV SHDN
20X
PLL
GND
V
DD
3.3V
0.1μF
0.1μF
22732 TA01
0
10
20
30
FREQUENCY (MHz)
40
22732
G04
PAT1 PAT0 SCRAM SRR1 SRR0
22732f
1

技术资料推荐更多

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1252  477  1815  354  287  26  10  37  8  6 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved