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LTC2272CUJ-PBF

产品描述16-Bit, 80Msps/65Msps Serial Output ADC
文件大小765KB,共44页
制造商Linear ( ADI )
官网地址http://www.analog.com/cn/index.html
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LTC2272CUJ-PBF概述

16-Bit, 80Msps/65Msps Serial Output ADC

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FEATURES
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LTC2273/LTC2272
16-Bit, 80Msps/65Msps
Serial Output ADC
DESCRIPTION
The LTC
®
2273/LTC2272 are 80Msps/65Msps, 16-bit A/D
converters with a high speed serial interface. They are
designed for digitizing high frequency, wide dynamic
range signals with an input bandwidth of 700MHz. The
input range of the ADC can be optimized using the PGA
front end. The output data is serialized according to the
JEDEC serial interface for data converters specification
(JESD204).
The LTC2273/LTC2272 are perfect for demanding applica-
tions where it is desirable to isolate the sensitive analog
circuits from the noisy digital logic. The AC performance
includes a 77.7dB Noise Floor and 100dB spurious free
dynamic range (SFDR). Ultra low internal jitter of 80fs
RMS allows undersampling of high input frequencies
with excellent noise performance. Maximum DC specs
include ±4.5LSB INL and ±1LSB DNL (no missing codes)
over temperature.
The encode clock inputs, ENC
+
and ENC
, may be driven
differentially or single-ended with a sine wave, PECL,
LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer
allows high performance at full speed with a wide range
of clock duty cycles.
L,
LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
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High Speed Serial Interface (JESD204)
Sample Rate: 80Msps/65Msps
77.7dBFS Noise Floor
100dB SFDR
SFDR >90dB at 140MHz (1.5V
P-P
Input Range)
PGA Front End (2.25V
P-P
or 1.5V
P-P
Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Single 3.3V Supply
Power Dissipation: 1100mW/990mW
Clock Duty Cycle Stabilizer
Pin Compatible Family
105Msps: LTC2274
80Msps: LTC2273
65Msps: LTC2272
40-Pin 6mm
×
6mm QFN Package
APPLICATIONS
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Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
TYPICAL APPLICATION
3.3V
SENSE
V
CM
1.25V
COMMON MODE
BIAS VOLTAGE
INTERNAL ADC
REFERENCE
GENERATOR
FAM
SYNC
+
8B/10B
ENCODER
16
20
SYNC
OV
DD
1.2V TO 3.3V
0.1μF
50Ω
A
IN +
ANALOG
INPUT
A
IN
ASIC OR FPGA
128k Point FFT, f
IN
= 4.93MHz,
–1dBFS, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
2.2μF
50Ω
AMPLITUDE (dBFS)
CMLOUT
+
+
SERIAL
RECEIVER
+
S/H
AMP
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
ENC
+
ENC
16-BIT
PIPELINED
ADC CORE
SERIALIZER
CORRECTION
LOGIC
CMLOUT
SCRAMBLER/
PATTERN
GENERATOR
PGA DITH MSBINV SHDN
20X
PLL
GND
V
DD
3.3V
0.1μF
0.1μF
22732 TA01
0
10
20
30
FREQUENCY (MHz)
40
22732
G04
PAT1 PAT0 SCRAM SRR1 SRR0
22732f
1

 
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