pling 14-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. They are perfect
for demanding communications applications with AC
performance that includes 73.4dB SNR and 85dB spurious
free dynamic range (SFDR). Ultralow jitter of 0.17ps
RMS
allows undersampling of IF frequencies with excellent
noise performance.
DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typi-
cal) and no missing codes over temperature. The transition
noise is a low 1.2LSB
RMS
.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC
+
and ENC
–
inputs may be driven differentially
or single ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L,
LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
73.4dB SNR
85dB SFDR
Low Power: 127mW/106mW/89mW
Single 1.8V Supply
CMOS, DDR CMOS or DDR LVDS Outputs
Selectable Input Ranges: 1V
P-P
to 2V
P-P
800MHz Full-Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm
×
6mm) QFN Package
APPLICATIONS
n
n
n
n
n
n
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
TYPICAL APPLICATION
2-Tone FFT, f
IN
= 70MHz and 75MHz
1.8V
V
DD
1.2V
TO 1.8V
OV
DD
0
–10
–20
–30
AMPLITUDE (dBFS)
–40
–50
–60
–70
–80
+
ANALOG
INPUT
INPUT
S/H
–
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
D13
CMOS
•
OR
•
LVDS
•
D0
OGND
CLOCK/DUTY
CYCLE
CONTROL
GND
226114 TA01a
–90
–100
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
60
226114 TA01b
125MHz
CLOCK
226114f
1
LTC2261-14
LTC2260-14/LTC2259-14
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages (V
DD
, OV
DD
) ....................... –0.3V to 2V
Analog Input Voltage (A
IN+
, A
IN–
,
PAR/SER, SENSE) (Note 3) ...........–0.3V to (V
DD
+ 0.2V)
Digital Input Voltage (ENC
+
, ENC
–
,
CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range:
LTC2261C, LTC2260C, LTC2259C............. 0°C to 70°C
LTC2261I, LTC2260I, LTC2259I ............ –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATIONS
D12_13
D10_11
SENSE
FULL-RATE CMOS OUTPUT MODE
TOP VIEW
V
REF
DNC
V
CM
D13
D12
D11
D10
V
DD
OF
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
SENSE
V
REF
DNC
DNC
DNC
30 D8_9
29 DNC
28 CLKOUT
+
27 CLKOUT
–
41
26 OV
DD
25 OGND
24 D6_7
23 DNC
22 D4_5
21 DNC
11 12 13 14 15 16 17 18 19 20
CS
DNC
D0_1
DNC
SDO
SCK
SDI
D2_3
ENC
+
ENC
–
V
CM
V
DD
OF
40 39 38 37 36 35 34 33 32 31
A
IN+
1
A
IN–
2
GND 3
REFH 4
REFH 5
REFL 6
REFL 7
PAR/SER 8
V
DD
9
V
DD
10
11 12 13 14 15 16 17 18 19 20
CS
SDO
SCK
D0
D1
D2
ENC
+
ENC
–
SDI
D3
41
30 D9
29 D8
28 CLKOUT
+
27
CLKOUT
–
A
IN+
1
A
IN–
2
GND 3
REFH 4
REFH 5
REFL 6
REFL 7
PAR/SER 8
V
DD
9
V
DD
10
40 39 38 37 36 35 34 33 32 31
26 OV
DD
25 OGND
24 D7
23 D6
22 D5
21 D4
UJ PACKAGE
40-LEAD (6mm 6mm) PLASTIC QFN
UJ PACKAGE
40-LEAD (6mm 6mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
T
JMAX
= 150°C,
θ
JA
= 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
D12_13
+
D12_13
–
D10_11
+
D2_3
–
D10_11
–
30 D8_9
+
29 D8_9
–
28 CLKOUT
+
27 CLKOUT
–
41
26 OV
DD
25 OGND
24 D6_7
+
23 D6_7
–
22 D4_5
+
21 D4_5
–
11 12 13 14 15 16 17 18 19 20
CS
ENC
+
ENC
–
SDO
SCK
SDI
D0_1
–
D0_1
+
D2_3
+
SENSE
V
REF
V
CM
V
DD
OF
+
OF
–
40 39 38 37 36 35 34 33 32 31
A
IN+
1
A
IN–
2
GND 3
REFH 4
REFH 5
REFL 6
REFL 7
PAR/SER 8
V
DD
9
V
DD
10
UJ PACKAGE
40-LEAD (6mm 6mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
226114f
2
LTC2261-14
LTC2260-14/LTC2259-14
ORDER INFORMATION
LEAD FREE FINISH
LTC2261CUJ-14#PBF
LTC2261IUJ-14#PBF
LTC2260CUJ-14#PBF
LTC2260IUJ-14#PBF
LTC2259CUJ-14#PBF
LTC2259IUJ-14#PBF
TAPE AND REEL
LTC2261CUJ-14#TRPBF
LTC2261IUJ-14#TRPBF
LTC2260CUJ-14#TRPBF
LTC2260IUJ-14#TRPBF
LTC2259CUJ-14#TRPBF
LTC2259IUJ-14#TRPBF
PART MARKING*
LTC2261UJ-14
LTC2261UJ-14
LTC2260UJ-14
LTC2260UJ-14
LTC2259UJ-14
LTC2259UJ-14
PACKAGE DESCRIPTION
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
LTC2261-14
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Transition Noise
Internal Reference
External Reference
External Reference
Differential Analog Input
(Note 7)
Internal Reference
External Reference
CONDITIONS
l
l
l
l
LTC2260-14
MIN
14
–3.75
–0.9
–9
–1.5
TYP
±1
±0.3
±1.5
±1.5
±0.4
±20
±30
±10
1.2
MAX
3.75
0.9
9
1.5
14
LTC2259-14
MIN
–3.5
–0.9
–9
–1.5
TYP
±1
±0.3
±1.5
±1.5
±0.4
±20
±30
±10
1.2
MAX
3.5
0.9
9
1.5
UNITS
Bits
LSB
LSB
mV
%FS
%FS
μV/°C
ppm/°C
ppm/°C
LSB
RMS
MIN
14
TYP
±1
±0.3
±1.5
±1.5
±0.4
±20
±30
±10
1.2
MAX
3.75
0.9
9
1.5
Differential Analog Input (Note 6)
l
–3.75
–0.9
–9
–1.5
226114f
3
LTC2261-14
LTC2260-14/LTC2259-14
ANALOG INPUT
SYMBOL PARAMETER
V
IN
V
IN(CM)
V
SENSE
I
INCM
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
+ A
IN–
)/2
Analog Input Common Mode Current
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
1.7V < V
DD
< 1.9V
Differential Analog Input (Note 8)
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
0 < A
IN+
, A
IN–
< V
DD
, No Encode
0 < PAR/SER < V
DD
0.625 < SENSE < 1.3V
l
l
l
l
l
l
MIN
V
CM
– 100mV
0.625
TYP
1 to 2
V
CM
1.250
155
130
100
MAX
V
CM
+ 100mV
1.300
UNITS
V
P-P
V
V
μA
μA
μA
External Voltage Reference Applied to SENSE External Reference Mode
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW-3B
Analog Input Leakage Current
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
–1
–3
–6
0
0.17
80
1
3
6
μA
μA
μA
ns
ps
RMS
dB
MHz
Figure 6 Test Circuit
800
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
LTC2261-14
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
CONDITIONS
5MHz Input
70MHz Input
140MHz Input
l
DYNAMIC ACCURACY
LTC2260-14
MIN
71.3
TYP
73.4
73.2
72.7
88
85
82
90
90
90
73
72.6
72
MAX
LTC2259-14
MIN
70.9
TYP
73.1
72.9
72.4
88
85
82
90
90
90
72.9
72.6
72
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
MIN
71.3
TYP
73.4
73.2
72.7
88
85
82
90
90
90
73
72.6
72
MAX
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
70MHz Input
140MHz Input
l
76
76
79
l
85
83
85
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
l
70.2
70.2
70.4
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400μA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
–600μA < I
OUT
< 1mA
I
OUT
= 0
CONDITIONS
I
OUT
= 0
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
MIN
0.5 • V
DD
– 25mV
TYP
0.5 • V
DD
±25
4
1.225
1.250
±25
7
0.6
1.275
MAX
0.5 • V
DD
+ 25mV
UNITS
V
ppm/°C
Ω
V
ppm/°C
Ω
mV/V
226114f
4
LTC2261-14
LTC2260-14/LTC2259-14
DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER
ENCODE INPUTS (ENC
+
, ENC
–
)
Differential Encode Mode (ENC
–
Not Tied to GND)
V
ID
V
ICM
V
IN
R
IN
C
IN
V
IH
V
IL
V
IN
R
IN
C
IN
V
IH
V
IL
I
IN
C
IN
R
OL
I
OH
C
OUT
Differential Input Voltage
Common Mode Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
(Note 8)
Internally Set
Externally Set (Note 8)
ENC
+
, ENC
–
to GND
(See Figure 10)
(Note 8)
V
DD
= 1.8V
V
DD
= 1.8V
ENC
+
to GND
(See Figure 11)
(Note 8)
V
DD
= 1.8V
V
DD
= 1.8V
V
IN
= 0V to 3.6V
(Note 8)
V
DD
= 1.8V, SDO = 0V
SDO = 0V to 3.6V
(Note 8)
l
l
l
l
l
l
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
MIN
TYP
MAX
UNITS
0.2
1.2
1.1
0.2
10
3.5
1.2
0.6
0
30
3.5
1.3
0.6
–10
3
200
–10
4
10
10
3.6
1.6
3.6
V
V
V
V
kΩ
pF
V
V
V
kΩ
pF
V
V
μA
pF
Ω
μA
pF
Single-Ended Encode Mode (ENC
–
Tied to GND)
DIGITAL INPUTS (CS, SDI, SCK)
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port(j,k,cp,r,s:in std_logic;
q,qb :out std_logic);
end jkff;
architecture rtl of jkff is
signal q_ ......
据国外媒体报道，英特尔将处理器价格最高下调31%，但降价整体来说是有限的。 根据英特尔7月20日的新定价单来看，Core 2 Duo E8500(3.16GHz)价格降幅最高，从266美元下调至183美元，降幅达31%；Core 2 Duo E7200 (2.53GHz)次之，从133美元下调至113美元，降幅15%。 其他降价处理器还有四核Q6600(2.4GHz)，从224美...[详细]
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