LTC1407-1/LTC1407A-1
Serial 12-Bit/14-Bit, 3Msps
Simultaneous Sampling
ADCs with Shutdown
FEATURES
s
s
s
s
s
s
DESCRIPTIO
s
s
s
s
s
s
3Msps Sampling ADC with Two Simultaneous
Differential Inputs
1.5Msps Throughput per Channel
Low Power Dissipation: 14mW (Typ)
3V Single Supply Operation
±1.25V
Differential Input Range
Pin Compatible 0V to 2.5V Input Range Version
(LTC1407/LTC1407A)
2.5V Internal Bandgap Reference with External
Overdrive
3-Wire Serial Interface
Sleep (10µW) Shutdown Mode
Nap (3mW) Shutdown Mode
80dB Common Mode Rejection at 100kHz
Tiny 10-Lead MS Package
The LTC
®
1407-1/LTC1407A-1 are 12-bit/14-bit, 3Msps
ADCs with two 1.5Msps simultaneously sampled differen-
tial inputs. The devices draw only 4.7mA from a single 3V
supply and come in a tiny 10-lead MS package. A Sleep
shutdown feature lowers power consumption to 10µW.
The combination of speed, low power and tiny package
makes the LTC1407-1/LTC1407A-1 suitable for high speed,
portable applications.
The LTC1407-1/LTC1407A-1 contain two separate differ-
ential inputs that are sampled simultaneously on the rising
edge of the CONV signal. These two sampled inputs are
then converted at a rate of 1.5Msps per channel.
The 80dB common mode rejection allows users to elimi-
nate ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert –1.25V to 1.25V bipolar inputs differ-
entially. The absolute voltage swing for CH0
+
, CH0
–
, CH1
+
and CH1
–
extends from ground to the supply voltage.
The serial interface sends out the two conversion results in
32 clocks for compatibility with standard serial interfaces.
, LTC and LT are registered trademarks of Linear Technology Corporation.
U.S. patent numbers 6084440, 6522187
APPLICATIO S
s
s
s
s
s
s
Telecommunications
Data Acquisition Systems
Uninterrupted Power Supplies
Multiphase Motor Control
I & Q Demodulation
Industrial Radio
BLOCK DIAGRA
CH0
+
1
10µF
3V
7
V
DD
LTC1407A-1
14-BIT LATCH
+
S&H
CH0
–
2
–
MUX
3Msps
14-BIT ADC
8
SDO
THD, 2nd, 3rd (dB)
CH1
+
4
+
S&H
14-BIT LATCH
THREE-
STATE
SERIAL
OUTPUT
PORT
CH1
–
5
–
V
REF
GND
2.5V
REFERENCE
10
TIMING
LOGIC
9
CONV
3
10µF
6
11
SCK
EXPOSED PAD
1407A1 BD
U
THD, 2nd and 3rd vs Input
Frequency for Differential
Input Signals
–44
–50
–56
–62
–68
–74
–80
–86
–92
–98
–104
0.1
1
FREQUENCY (MHz)
10
2nd
THD
3rd
20
14071 G22
W
U
14071f
1
LTC1407-1/LTC1407A-1
ABSOLUTE
(Notes 1, 2)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
CH0
+
1
CH0
–
2
V
REF
3
CH1
+
4
CH1
–
5
11
10
9
8
7
6
CONV
SCK
SDO
V
DD
GND
Supply Voltage (V
DD
) ................................................. 4V
Analog Input Voltage
(Note 3) ................................... – 0.3V to (V
DD
+ 0.3V)
Digital Input Voltage .................... – 0.3V to (V
DD
+ 0.3V)
Digital Output Voltage .................. – 0.3V to (V
DD
+ 0.3V)
Power Dissipation .............................................. 100mW
Operation Temperature Range
LTC1407C-1/LTC1407AC-1 ..................... 0°C to 70°C
LTC1407I-1/LTC1407AI-1 .................. – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
MSE PACKAGE
10-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 150°C/ W
EXPOSED PAD IS GND (PIN 11)
MUST BE SOLDERED TO PCB
LTC1407CMSE-1
LTC1407IMSE-1
LTC1407ACMSE-1
LTC1407AIMSE-1
MSE PART MARKING
LTBGT
LTBGV
LTBGW
LTBGX
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER CHARACTERISTICS
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Offset Error
Offset Match from CH0 to CH1
Gain Error
Gain Match from CH0 to CH1
Gain Tempco
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= 3V.
CONDITIONS
q
LTC1407-1
MIN TYP MAX
12
–2
–10
–5
q
q
q
LTC1407A-1
MIN TYP MAX
14
–4
–20
–10
–60
–10
±0.5
±2
±1
±10
±2
±15
±1
4
20
10
60
10
UNITS
Bits
LSB
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
(Notes 5, 17)
(Notes 4, 17)
(Note 17)
(Notes 4, 17)
(Note 17)
Internal Reference (Note 4)
External Reference
±0.25
±1
±0.5
±5
±1
±15
±1
2
10
5
30
5
–30
–5
A ALOG I PUT
SYMBOL PARAMETER
V
IN
V
CM
I
IN
C
IN
t
ACQ
t
AP
t
JITTER
t
SK
CMRR
The
q
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= 3V.
CONDITIONS
2.7V
≤
V
DD
≤
3.3V
MIN
TYP
–1.25 to 1.25
0 to V
DD
q
MAX
UNITS
V
V
Analog Differential Input Range (Notes 3, 8, 9)
Analog Common Mode + Differential
Input Range (Note 10)
Analog Input Leakage Current
Analog Input Capacitance
Sample-and-Hold Acquisition Time
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Sample-and-Hold Aperture Skew from CH0 to CH1
Analog Input Common Mode Rejection Ratio
1
13
39
1
0.3
200
(Note 18)
(Note 6)
q
f
IN
= 1MHz, V
IN
= 0V to 3V
f
IN
= 100MHz, V
IN
= 0V to 3V
–60
–15
2
U
µA
pF
ns
ns
ps
ps
dB
dB
14071f
W
U
U
W W
W
U
U
U
LTC1407-1/LTC1407A-1
DY A IC ACCURACY
SYMBOL
SINAD
PARAMETER
Signal-to-Noise Plus
Distortion Ratio
The
q
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= 3V. Single ended signal drive CH0
+
/CH1
+
with
CHO
–
/CH1
–
= 1.5V DC. Differential signals drive both inputs of each channel with V
CM
= 1.5V DC.
CONDITIONS
100kHz Input Signal (Note 19)
750kHz Input Signal (Note 19)
100kHz Input Signal, External V
REF
= 3.3V,
V
DD
≥
3.3V (Note 19)
750kHz Input Signal, External V
REF
= 3.3V,
V
DD
≥
3.3V (Note 19)
100kHz First 5 Harmonics (Note 19)
750kHz First 5 Harmonics (Note 19)
100kHz Input Signal (Note 19)
750kHz Input Signal (Note 19)
0.625V
P-P
1.4MHz Summed with 0.625V
P-P
, 1.56MHz
into CH0
+
and Inverted into CHO
–
. Also Applicable
to CH1
+
and CH1
–
V
REF
= 2.5V (Note 17)
V
IN
= 2.5V
P-P
, SDO = 11585LSB
P-P
(–3dBFS) (Note 15)
S/(N + D)
≥
68dB
q
THD
SFDR
IMD
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
V
REF
Output Voltage
V
REF
Output Tempco
V
REF
Line Regulation
V
REF
Output Resistance
V
REF
Settling Time
CONDITIONS
I
OUT
= 0
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
OZ
C
OZ
I
SOURCE
I
SINK
PARAMETER
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage D
OUT
Hi-Z Output Capacitance D
OUT
Output Short-Circuit Source Current
Output Short-Circuit Sink Current
V
OUT
= 0V, V
DD
= 3V
V
OUT
= V
DD
= 3V
CONDITIONS
V
DD
= 3.3V
V
DD
= 2.7V
V
IN
= 0V to V
DD
The
q
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= 3V.
MIN
q
q
q
U
U
U
W U
U
LTC1407-1
MIN TYP MAX
68
70.5
70.5
72.0
72.0
–87
–83
–87
–83
–82
LTC1407A-1
MIN TYP MAX
70
73.5
73.5
76.3
76.3
–90
–86
–90
–86
–82
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
Total Harmonic
Distortion
Spurious Free
Dynamic Range
Intermodulation
Distortion
Code-to-Code
Transition Noise
Full Power Bandwidth
Full Linear Bandwidth
q
–77
–80
0.25
50
5
1
50
5
LSB
RMS
MHz
MHz
U
T
A
= 25°C. V
DD
= 3V.
MIN
TYP
2.5
15
600
0.2
2
MAX
UNITS
V
ppm/°C
µV/V
Ω
ms
V
DD
= 2.7V to 3.6V, V
REF
= 2.5V
Load Current = 0.5mA
TYP
MAX
0.6
±10
UNITS
V
V
µA
pF
V
V
V
µA
pF
mA
mA
14071f
2.4
5
V
DD
= 3V, I
OUT
= – 200µA
V
DD
= 2.7V, I
OUT
= 160µA
V
DD
= 2.7V, I
OUT
= 1.6mA
V
OUT
= 0V to V
DD
q
q
q
2.5
2.9
0.05
0.10
1
20
15
0.4
±10
3
LTC1407-1/LTC1407A-1
POWER REQUIRE E TS
SYMBOL
V
DD
I
DD
PARAMETER
Supply Voltage
Supply Current
The
q
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= 3V.
CONDITIONS
Active Mode, f
SAMPLE
= 1.5Msps
Nap Mode
Sleep Mode (LTC1407)
Sleep Mode (LTC1407A)
Active Mode with SCK in Fixed State (Hi or Lo)
q
q
PD
Power Dissipation
The
q
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
DD
= 3V.
SYMBOL
f
SAMPLE(MAX)
t
THROUGHPUT
t
SCK
t
CONV
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
12
PARAMETER
Maximum Sampling Frequency per Channel
(Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
Conversion Time
Minimum Positive or Negative SCLK Pulse Width
CONV to SCK Setup Time
SCK Before CONV
Minimum Positive or Negative CONV Pulse Width
SCK to Sample Mode
CONV to Hold Mode
32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period)
Minimum Delay from SCK to Valid Bits 0 Through 11
SCK to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
Settling Time After Sleep-to-Wake Transition
CONDITIONS
q
q
TI I G CHARACTERISTICS
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground GND.
Note 3:
When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4:
Offset and range specifications apply for a single-ended CH0
+
or
CH1
+
input with CH0
–
or CH1
–
grounded and using the internal 2.5V
reference.
Note 5:
Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6:
Guaranteed by design, not subject to test.
Note 7:
Recommended operating conditions.
Note 8:
The analog input range is defined for the voltage difference
between CH0
+
and CH0
–
or CH1
+
and CH1
–
. Performance is specified with
CHO
–
= 1.5V DC while driving CHO
+
and with CH1
–
= 1.5V DC while
driving CH1
+
.
Note 9:
The absolute voltage at CH0
+
, CH0
–
, CH1
+
and CH1
–
must be
within this range.
4
U W
MIN
2.7
TYP
4.7
1.1
2.0
2.0
12
MAX
3.6
7.0
1.5
15
10
UNITS
V
mA
mA
µA
µA
mW
UW
MIN
1.5
TYP
MAX
UNITS
MHz
ns
ns
SCLK cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
(Note 16)
(Note 6)
(Note 6)
(Notes 6, 10)
(Note 6)
(Note 6)
(Note 6)
(Notes 6, 11)
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 14)
q
19.6
32
2
3
0
4
4
1.2
45
8
6
2
667
10000
34
2
Note 10:
If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13:
The time period for acquiring the input signal is started by the
32nd rising clock and it is ended by the rising edge of CONV.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15:
The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
P-P
input sine wave.
Note 16:
Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17:
The LTC1407A-1 is measured and specified with 14-bit
Resolution (1LSB = 152µV) and the LTC1407-1 is measured and specified
with 12-bit Resolution (1LSB = 610µV).
Note 18:
The sampling capacitor at each input accounts for 4.1pF of the
input capacitance.
Note 19:
Full-scale sinewaves are fed into the noninverting inputs while
the inverting inputs are kept at 1.5V DC.
14071f
LTC1407-1/LTC1407A-1
TYPICAL PERFOR A CE CHARACTERISTICS
ENOBs and SINAD
vs Input Sinewave Frequency
12.0
11.5
11.0
ENOBs (BITS)
V
DD
= 3V, T
A
= 25°C. Single ended signals drive
+CH0/+CH1 with –CH0/–CH1 = 1.5V DC, differential signals drive both inputs with V
CM
= 1.5V DC (LTC1407A-1)
THD, 2nd and 3rd
vs Input Frequency
74
71
68
65
62
59
56
53
1
10
FREQUENCY (MHz)
50
100
14071 G01
10.0
9.5
9.0
8.5
8.0
0.1
–74
–80
–86
–92
–98
–104
0.1
THD
3rd
2nd
SFDR (dB)
100
14071 G02
10.5
THD, 2nd, 3rd (dB)
SNR vs Input Frequency
74
71
68
12.0
11.5
11.0
ENOBs (BITS)
SNR (dB)
65
62
59
56
53
50
0.1
1
10
FREQUENCY (MHz)
100
14071 G04
10.5
10.0
9.5
9.0
8.5
8.0
0.1
1
10
FREQUENCY (MHz)
65
62
59
56
53
50
100
14071 G21
THD, 2nd, 3rd (dB)
SFDR vs Input Frequency for
Differential Input Signals
104
98
92
MAGNITUDE (dB)
MAGNITUDE (dB)
86
SFDR (dB)
80
74
68
62
56
50
44
0.1
1
10
FREQUENCY (MHz)
100
14071 G23
U W
SFDR vs Input Frequency
104
98
92
86
80
74
68
62
56
50
–44
–50
–56
–62
–68
SINAD (dB)
1
10
FREQUENCY (MHz)
44
0.1
1
10
FREQUENCY (MHz)
100
14071 G03
ENOBs and SINAD vs Input
Sinewave Frequency for
Differential Input Signals
74
71
68
THD, 2nd and 3rd vs Input
Frequency for Differential Input
Signals
–44
–50
–56
–62
–68
–74
–80
–86
–92
–98
–104
0.1
1
FREQUENCY (MHz)
10
2nd
THD
3rd
SINAD (dB)
20
14071 G22
98kHz Sine Wave 4096 Point
FFT Plot
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
100
200 300 400 500
FREQUENCY (kHz)
600
700
14071 G05
748kHz Sine Wave 4096 Point
FFT Plot
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
100
200 300 400 500
FREQUENCY (kHz)
600
700
14071 G06
14071f
5
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