LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Rev. 03 — 7 April 2010
Product data sheet
1. General description
The LPC2939 combine an ARM968E-S CPU core with two integrated TCM blocks
operating at frequencies of up to 125 MHz, Full-speed USB 2.0 Host/OTG/Device
controller, CAN and LIN, 56 kB SRAM, 768 kB flash memory, external memory interface,
three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at
consumer, industrial, medical, and communication markets. To optimize system power
consumption, the LPC2939 has a very flexible Clock Generation Unit (CGU) that provides
dynamic clock gating and scaling.
2. Features and benefits
ARM968E-S processor running at frequencies of up to 125 MHz maximum.
Multilayer AHB system bus at 125 MHz with four separate layers.
On-chip memory:
Two Tightly Coupled Memories (TCM), 32 kB Instruction (ITCM), 32 kB Data TCM
(DTCM)
Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB
SRAM
8 kB ETB SRAM, also usable for code execution and data
768 kB high-speed flash program memory
16 kB true EEPROM, byte-erasable/programmable
Dual-master, eight-channel GPDMA controller on the AHB multilayer matrix which can
be used with the SPI interfaces and the UARTs, as well as for memory-to-memory
transfers including the TCM memories
External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data
bus; up to 24-bit address bus
Serial interfaces:
USB 2.0 full-speed Host/OTG/Device controller with dedicated DMA controller and
on-chip device PHY
Two-channel CAN controller supporting FullCAN and extensive message filtering
Two LIN master controllers with full hardware support for LIN communication. The
LIN interface can be configured as UART to provide two additional UART
interfaces.
Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, modem
control, and RS-485/EIA-485 (9-bit) support
Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;
Tx FIFO and Rx FIFO
Two I
2
C-bus interfaces
NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Other peripherals:
One 10-bit ADC with 5.0 V measurement range and eight input channels with
conversion times as low as 2.44
s
per channel
Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide an
additional 16 analog inputs with conversion times as low as 2.44
s
per channel.
Each channel provides a compare function to minimize interrupts.
Multiple trigger-start option for all ADCs: timer, PWM, other ADC, and external
signal input
Four 32-bit timers each containing four capture-and-compare registers linked to
I/Os
Four six-channel PWMs (Pulse-Width Modulators) with capture and trap
functionality
Two dedicated 32-bit timers to schedule and synchronize PWM and ADC
Quadrature encoder interface that can monitor one external quadrature encoder
32-bit watchdog with timer change protection, running on safe clock
Up to 152 general-purpose I/O pins with programmable pull-up, pull-down, or bus
keeper
Vectored Interrupt Controller (VIC) with 16 priority levels
Up to 22 level-sensitive external interrupt pins, including USB, CAN and LIN wake-up
features
Configurable clock-out pin for driving external system clocks
Processor wake-up from power-down via external interrupt pins and CAN or LIN
activity
Flexible Reset Generator Unit (RGU) able to control resets of individual modules
Flexible Clock-Generation Unit (CGU) able to control clock frequency of individual
modules:
On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to
provide a Safe_Clock source for system monitoring
On-chip crystal oscillator with a recommended operating range from 10 MHz to
25 MHz. PLL input range 10 MHz to 25 MHz.
On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz
Generation of up to 11 base clocks
Seven fractional dividers
Second, dedicated CGU with its own PLL generates USB clocks and a configurable
clock output
Highly configurable system Power Management Unit (PMU):
clock control of individual modules
allows minimization of system operating power consumption in any configuration
Standard ARM test and debug interface with real-time in-circuit emulator
Boundary-scan test supported
ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for
application code and data storage
Dual power supply:
CPU operating voltage: 1.8 V
5 %
I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V
208-pin LQFP package
LPC2939_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2010
2 of 99
NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
40 C
to +85
C
ambient operating temperature range
3. Ordering information
Table 1.
Ordering information
Package
Name
LPC2939FBD208
Description
Version
SOT459-1
LQFP208 plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm
Type number
3.1 Ordering options
Table 2.
Part options
Flash
memory
SRAM
SMC
USB
UART
LIN 2.0/
Host/
RS-485/ UART
OTG/
modem
device
yes
2
2
CAN
Package
Type number
LPC2939FBD208
768 kB
56 kB +
32-bit
2
32 kB TCM
2
LQFP208
LPC2939_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2010
3 of 99
NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
4. Block diagram
JTAG
interface
LPC2939
ITCM
32 kB
TEST/DEBUG
INTERFACE
8 kB SRAM
DTCM
32 kB
ARM968E-S
1 master
2 slaves
master
master
GPDMA CONTROLLER
VECTORED
INTERRUPT
CONTROLLER
CLOCK
GENERATION
UNIT
RESET
GENERATION
UNIT
POWER
MANAGEMENT
UNIT
TIMER0/1 MTMR
PWM0/1/2/3
3.3 V ADC1/2
5 V ADC0
QUADRATURE
ENCODER
AHB TO DTL
BRIDGE
slave
slave
GPDMA REGISTERS
master
AHB TO DTL
BRIDGE
slave
slave
USB HOST/OTG/DEVICE
CONTROLLER
power, clock, and
reset subsystem
slave
EXTERNAL STATIC
MEMORY CONTROLLER
EMBEDDED SRAM 16 kB
slave
AHB
MULTI-
LAYER
MATRIX
slave
EMBEDDED SRAM 32 kB
slave
EMBEDDED FLASH
768 kB
slave
AHB TO APB
BRIDGE
general subsystem
SYSTEM CONTROL
EVENT ROUTER
CHIP FEATURE ID
AHB TO APB
BRIDGE
AHB TO APB
BRIDGE
slave
peripheral subsystem
16 kB
EEPROM
AHB TO APB
BRIDGE
slave
MSC subsystem
slave
GENERAL PURPOSE I/O
PORTS 0/1/2/3/4/5
TIMER0/1/2/3
SPI0/1/2
RS-485 UART0/1
WDT
CAN0/1
GLOBAL
ACCEPTANCE
FILTER
UART/LIN0/1
I
2
C0/1
networking subsystem
002aae254
Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA.
Fig 1.
LPC2939 block diagram
LPC2939_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2010
4 of 99
NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
5. Pinning information
5.1 Pinning
208
157
156
105
104
53
002aae253
1
LPC2939FBD208
52
Fig 2.
Pin configuration for LQFP208 package
5.2 Pin description
5.2.1 General description
The LPC2939 uses five ports: port 0 and port 1 with 32 pins, ports 2 with 28 pins each,
port 3 with 16 pins, port 4 with 24 pins, and port 5 with 20 pins. The pin to which each
function is assigned is controlled by the SFSP registers in the SCU. The functions
combined on each port pin are shown in the pin description tables in this section.
5.2.2 LQFP208 pin assignment
Table 3.
Pin name
LQFP208 pin assignment
Pin
Description
Function 0
(default)
TDO
P2[21]/SDI2/
PCAP2[1]/D19
P0[24]/TXD1/
TXDC1/SCS2[0]
P0[25]/RXD1/
RXDC1/SDO2
P0[26]/TXD1/SDI2
P0[27]/RXD1/SCK2
P0[28]/CAP0[0]/
MAT0[0]
P0[29]/CAP0[1]/
MAT0[1]
V
DD(IO)
P2[22]/SCK2/
PCAP2[2]/D20
LPC2939_3
Function 1
Function 2
Function 3
1
[1]
2
[1]
3
[1]
4
[1]
5
[1]
6
[1]
7
[1]
8
[1]
9
10
[1]
IEEE 1149.1 test data out
GPIO 2, pin 21
GPIO 0, pin 24
GPIO 0, pin 25
GPIO 0, pin 26
GPIO 0, pin 27
GPIO 0, pin 28
GPIO 0, pin 29
SPI2 SDI
UART1 TXD
UART1 RXD
-
-
-
-
PWM2 CAP1
CAN1 TXD
CAN1 RXD
UART1 TXD
UART1 RXD
TIMER0 CAP0
TIMER0 CAP1
EXTBUS D19
SPI2 SCS0
SPI2 SDO
SPI2 SDI
SPI2 SCK
TIMER0 MAT0
TIMER0 MAT1
3.3 V power supply for I/O
GPIO 2, pin 22
SPI2 SCK
PWM2 CAP2
EXTBUS D20
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2010
5 of 99
微控制器 MCU
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