LPC2290
16/32-bit ARM microcontroller with CAN, 10-bit ADC and
external memory interface
Rev. 03 — 16 November 2006
Product data sheet
1. General description
The LPC2290 microcontroller is based on a 16/32-bit ARM7TDMI-S CPU with real-time
emulation and embedded trace support. For critical code size applications, the alternative
16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.
With its 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit
ADC, two advanced CAN channels, PWM channels and up to nine external interrupt pins
this microcontroller is particularly suitable for automotive and industrial control
applications as well as medical systems and fault-tolerant maintenance buses. The
LPC2290 provides up to 76 GPIOs depending on bus configuration. With a wide range of
additional serial communications interfaces, it is also suited for communication gateways
and protocol converters as well as many other general-purpose applications.
Remark:
Throughout the data sheet, the term ‘LPC2290’ will apply to devices with and
without the /01 suffix. New devices will use the /01 suffix to differentiate from the original
devices only when necessary.
2. Features
2.1 Enhancements introduced with LPC2290/01 device
I
CPU clock up to 72 MHz and 64 kB of on-chip static RAM.
I
Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original
LPC2290. A port pin can be read at any time regardless of its function.
I
Dedicated result registers for ADC reduce interrupt overhead.
I
UART0/1 include fractional baud rate generator, auto-bauding capabilities and
handshake flow-control fully implemented in hardware.
I
SSP serial controller supporting SPI, 4-wire SSI, and Microwire buses.
2.2 Key features common for LPC2290 and LPC2290/01
I
16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package.
I
16/64 kB on-chip static RAM.
I
Serial bootloader using UART0 provides in-system download and programming
capabilities.
I
EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the
on-chip RealMonitor software as well as high-speed real-time tracing of instruction
execution.
I
Two interconnected CAN interfaces with advanced acceptance filters. Additional serial
interfaces include two UARTs (16C550), Fast I
2
C-bus (400 kbit/s) and two SPIs.
NXP Semiconductors
LPC2290
16/32-bit ARM microcontroller with external memory interface
I
Eight channel 10-bit ADC with conversion time as low as 2.44
µs.
I
Two 32-bit timers (with four capture and four compare channels), PWM unit (six
outputs), Real-Time Clock (RTC) and watchdog.
I
Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.
I
Configurable external memory interface with up to four banks, each up to 16 MB and
8/16/32-bit data width.
I
Up to 76 general purpose I/O pins (5 V tolerant). Up to nine edge/level sensitive
external interrupt pins available.
I
60/72 MHz maximum CPU clock available from programmable on-chip PLL with
settling time of 100
µs.
I
On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
I
Power saving modes include Idle and Power-down.
I
Processor wake-up from Power-down mode via external interrupt.
I
Individual enable/disable of peripheral functions for power optimization.
I
Dual power supply:
N
CPU operating voltage range of 1.65 V to 1.95 V (1.8 V
±
0.15 V).
N
I/O power supply range of 3.0 V to 3.6 V (3.3 V
±
10 %) with 5 V tolerant I/O pads.
3. Ordering information
Table 1.
Ordering information
Package
Name
LPC2290FBD144
LPC2290FBD144/01
LQFP144
LQFP144
Description
plastic low profile quad flat package;
144 leads; body 20
×
20
×
1.4 mm
plastic low profile quad flat package;
144 leads; body 20
×
20
×
1.4 mm
Version
SOT486-1
SOT486-1
Type number
3.1 Ordering options
Table 2.
Ordering options
RAM
16 kB
CAN
Enhancements
Temperature range
−40 °C
to +85
°C
−40 °C
to +85
°C
2 channels None
2 channels Higher CPU clock, more
on-chip SRAM, Fast I/Os,
improved UARTs, added SSP,
upgraded ADC
Type number
LPC2290FBD144
LPC2290FBD144/01 64 kB
LPC2290_3
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 16 November 2006
2 of 41
NXP Semiconductors
LPC2290
16/32-bit ARM microcontroller with external memory interface
4. Block diagram
TMS
(1)
TDI
(1)
TRST
(1)
TCK
(1)
TDO
(1)
XTAL2
RST
XTAL1
LPC2290
LPC2290/01
P0[31:0]
P1[31:16], P1[1:0]
TEST/DEBUG
INTERFACE
EMULATION TRACE
MODULE
PLL
system
clock
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
ARM7TDMI-S
FAST GENERAL
PURPOSE I/O
(3)
ARM7 local
bus
AHB BRIDGE
AMBA Advanced High-performance
Bus(AHB)
INTERNAL
SRAM
CONTROLLER
AHB
DECODER
AHB TO APB
BRIDGE
APB
DIVIDER
CS3 to CS0
(2)
A23 to A0
(2)
BLS3 to BLS0
(2)
OE, WE
(2)
D31 to D0
(2)
SCL
SDA
SCK0, SCK1
16/64 kB
SRAM
EXTERNAL MEMORY
CONTROLLER
Advanced
Peripheral Bus
(APB)
EINT3 to EINT0
EXTERNAL
INTERRUPTS
I
2
C-BUS SERIAL
INTERFACE
4
×
CAP0
4
×
CAP1
4
×
MAT0
4
×
MAT1
CAPTURE/
COMPARE
TIMER 0/TIMER 1
SPI AND SSP
(3)
SERIAL INTERFACES
0 AND 1
MOSI0, MOSI1
MISO0, MISO1
SSEL0, SSEL1
TXD0, TXD1
AIN3 to AIN0
A/D CONVERTER
AIN7 to AIN4
P0[30:0]
P1[31:16], P1[1:0]
P2[31:0]
P3[31:0]
PWM6 to PWM1
PWM0
WATCHDOG
TIMER
SYSTEM
CONTROL
GENERAL
PURPOSE I/O
CAN
UART0/UART1
RXD0, RXD1
DSR1, CTS1,
DCD1, RI1
TD2, TD1
RD2, RD1
REAL-TIME CLOCK
002aaa796
(1) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(2) Pins shared with GPIO.
(3) Available in LPC2290/01 only.
Fig 1. Block diagram
LPC2290_3
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 16 November 2006
3 of 41
NXP Semiconductors
LPC2290
16/32-bit ARM microcontroller with external memory interface
5. Pinning information
5.1 Pinning
144
109
108
1
LPC2290
36
37
72
73
002aaa797
Fig 2. LQFP144 pinning
LPC2290_3
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 16 November 2006
4 of 41
NXP Semiconductors
LPC2290
16/32-bit ARM microcontroller with external memory interface
5.2 Pin description
Table 3.
Symbol
P0.0 to P0.31
Pin description
Pin
Type
I/O
Description
Port 0:
Port 0 is a 32-bit bidirectional I/O port with individual direction controls
for each bit. The operation of port 0 pins depends upon the pin function
selected via the Pin Connect Block.
Pins 26 and 31 of port 0 are not available.
P0.0/TXD0/
PWM1
42
[1]
I/O
O
O
P0.1/RXD0/
PWM3/EINT0
49
[2]
I/O
I
O
I
P0.2/SCL/
CAP0.0
50
[3]
I/O
I/O
I
P0.3/SDA/
MAT0.0/EINT1
58
[3]
I/O
I/O
O
I
P0.4/SCK0/
CAP0.1
59
[1]
I/O
I/O
I
P0.5/MISO0/
MAT0.1
61
[1]
I/O
I/O
O
P0.6/MOSI0/
CAP0.2
68
[1]
I/O
I/O
I
P0.7/SSEL0/
PWM2/EINT2
69
[2]
I/O
I
O
I
P0.8/TXD1/
PWM4
75
[1]
I/O
O
O
P0.0 —
General purpose digital input/output pin.
TXD0 —
Transmitter output for UART0.
PWM1 —
Pulse Width Modulator output 1.
P0.1 —
General purpose digital input/output pin.
RXD0 —
Receiver input for UART0.
PWM3 —
Pulse Width Modulator output 3.
EINT0 —
External interrupt 0 input
P0.2 —
General purpose digital input/output pin.
SCL —
I
2
C-bus clock input/output. Open-drain output (for I
2
C-bus
compliance).
CAP0.0 —
Capture input for Timer 0, channel 0.
P0.3 —
General purpose digital input/output pin.
SDA —
I
2
C-bus data input/output. Open-drain output (for I
2
C-bus
compliance).
MAT0.0 —
Match output for Timer 0, channel 0.
EINT1 —
External interrupt 1 input.
P0.4 —
General purpose digital input/output pin.
SCK0 —
Serial clock for SPI0. SPI clock output from master or input to slave.
CAP0.1 —
Capture input for Timer 0, channel 1.
P0.5 —
General purpose digital input/output pin.
MISO0 —
Master In Slave OUT for SPI0. Data input to SPI master or data
output from SPI slave.
MAT0.1 —
Match output for Timer 0, channel 1.
P0.6 —
General purpose digital input/output pin.
MOSI0 —
Master Out Slave In for SPI0. Data output from SPI master or data
input to SPI slave.
CAP0.2 —
Capture input for Timer 0, channel 2.
P0.7 —
General purpose digital input/output pin.
SSEL0 —
Slave Select for SPI0. Selects the SPI interface as a slave.
PWM2 —
Pulse Width Modulator output 2.
EINT2 —
External interrupt 2 input.
P0.8 —
General purpose digital input/output pin.
TXD1 —
Transmitter output for UART1.
PWM4 —
Pulse Width Modulator output 4.
LPC2290_3
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 16 November 2006
5 of 41
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