LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and
8 kB SRAM; USB device
Rev. 02 — 6 May 2010
Product data sheet
1. General description
The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded
applications featuring a high level of integration and low power consumption. The ARM
Cortex-M3 is a next generation core that offers system enhancements such as enhanced
debug features and a higher level of support block integration.
The LPC1311/13/42/43 operate at CPU frequencies of up to 72 MHz. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branching.
The peripheral complement of the LPC1311/13/42/43 includes up to 32 kB of flash
memory, up to 8 kB of data memory, USB Device (LPC1342/43 only), one Fast-mode Plus
I
2
C-bus interface, one UART, four general purpose timers, and up to 42 general purpose
I/O pins.
2. Features and benefits
ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming
memory.
8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
Selectable boot-up: UART or USB (USB on LPC134x only).
On LPC134x: USB MSC and HID on-chip drivers.
Serial interfaces:
USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43
only).
UART with fractional baud rate generation, modem, internal FIFO, and
RS-485/EIA-485 support.
SSP controller with FIFO and multi-protocol capabilities.
I
2
C-bus interface supporting full I
2
C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
Other peripherals:
Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors.
Four general purpose counter/timers with a total of four capture inputs and 13
match outputs.
Programmable WatchDog Timer (WDT).
System tick timer.
Serial Wire Debug and Serial Wire Trace port.
High-current output driver (20 mA) on one pin.
High-current sink drivers (20 mA) on two I
2
C-bus pins in Fast-mode Plus.
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, and Deep power-down modes.
Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
Single power supply (2.0 V to 3.6 V).
10-bit ADC with input multiplexing among 8 pins.
GPIO pins can be used as edge and level sensitive interrupt sources.
Clock output function with divider that can reflect the system oscillator clock, IRC
clock, CPU clock, or the watchdog clock.
Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40 of
the functional pins.
Brownout detect with four separate thresholds for interrupt and one threshold for
forced reset.
Power-On Reset (POR).
Integrated oscillator with an operating range of 1 MHz to 25 MHz.
12 MHz internal RC oscillator trimmed to 1 % accuracy over the entire temperature
and voltage range that can optionally be used as a system clock.
Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.
System PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator or the internal RC
oscillator.
For USB (LPC1342/43), a second, dedicated PLL is provided.
Code Read Protection (CRP) with different security levels.
Unique device serial number for identification.
Available as 48-pin LQFP package and 33-pin HVQFN package.
3. Applications
eMetering
Lighting
Alarm systems
White goods
LPC1311_13_42_43_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 6 May 2010
2 of 60
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC1311FHN33 HVQFN33
LPC1313FBD48 LQFP48
LPC1313FHN33 HVQFN33
LPC1342FHN33 HVQFN33
LPC1343FBD48 LQFP48
LPC1343FHN33 HVQFN33
Description
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7
×
7
×
0.85 mm
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7
×
7
×
0.85 mm
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7
×
7
×
0.85 mm
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7
×
7
×
0.85 mm
Version
n/a
Type number
LQFP48: plastic low profile quad flat package; 48 leads; body 7
×
7
×
1.4 mm SOT313-2
n/a
n/a
LQFP48: plastic low profile quad flat package; 48 leads; body 7
×
7
×
1.4 mm SOT313-2
n/a
4.1 Ordering options
Table 2.
Ordering options for LPC1311/13/42/43
Flash
8 kB
32 kB
32 kB
16 kB
32 kB
32 kB
Total
SRAM
4 kB
8 kB
8 kB
4 kB
8 kB
8 kB
USB
-
-
-
Device
Device
Device
UART
RS-485
1
1
1
1
1
1
I
2
C/
Fast+
1
1
1
1
1
1
SSP
1
1
1
1
1
1
ADC
channels
8
8
8
8
8
8
Pins
33
48
33
33
48
33
Package
HVQFN33
LQFP48
HVQFN33
HVQFN33
LQFP48
HVQFN33
Type number
LPC1311FHN33
LPC1313FBD48
LPC1313FHN33
LPC1342FHN33
LPC1343FBD48
LPC1343FHN33
LPC1311_13_42_43_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 6 May 2010
3 of 60
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
5. Block diagram
XTALIN
XTALOUT
RESET
SWD
USB pins
LPC1311/13/42/43
USB PHY
(1)
TEST/DEBUG
INTERFACE
IRC
WDO
ARM
CORTEX-M3
I-code
bus
D-code
bus
system
bus
USB DEVICE
CONTROLLER
(1)
POR
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
clocks and
controls
slave
ROM
CLKOUT
slave
AHB-LITE BUS
slave
SRAM
4/8 kB
GPIO ports
PIO0/1/2/3
HIGH-SPEED
GPIO
slave
slave
AHB TO
APB
BRIDGE
slave
FLASH
8/16/32 kB
RXD
TXD
DTR, DSR
(2)
, CTS,
DCD
(2)
, RI
(2)
, RTS
CT32B0_MAT[3:0]
CT32B0_CAP0
CT32B1_MAT[3:0]
CT32B1_CAP0
CT16B0_MAT[2:0]
CT16B0_CAP0
CT16B1_MAT[1:0]
CT16B1_CAP0
UART
10-bit ADC
AD[7:0]
SCK
SSEL
MISO
MOSI
SCL
SDA
SSP
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
I
2
C-BUS
WDT
IOCONFIG
SYSTEM CONTROL
002aae722
(1) LPC1342/43 only.
(2) LQFP48 package only.
Fig 1.
Block diagram
LPC1311_13_42_43_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 6 May 2010
4 of 60
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
6. Pinning information
6.1 Pinning
40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP
39 SWDIO/PIO1_3/AD4/CT32B1_MAT2
46 PIO1_6/RXD/CT32B0_MAT0
47 PIO1_7/TXD/CT32B0_MAT1
45 PIO1_5/RTS/CT32B0_CAP0
42 PIO1_11/AD7
38 PIO2_3/RI
48 PIO3_3
43 PIO3_2
PIO2_6
PIO2_0/DTR
RESET/PIO0_0
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE
V
SS
XTALIN
XTALOUT
V
DD
PIO1_8/CT16B1_CAP0
1
2
3
4
5
6
7
8
9
37 PIO3_1
36 PIO3_0
35 R/PIO1_2/AD3/CT32B1_MAT1
34 R/PIO1_1/AD2/CT32B1_MAT0
33 R/PIO1_0/AD1/CT32B1_CAP0
32 R/PIO0_11/AD0/CT32B0_MAT3
31 PIO2_11/SCK
30 PIO1_10/AD6/CT16B1_MAT1
29 SWCLK/PIO0_10/SCK/CT16B0_MAT2
28 PIO0_9/MOSI/CT16B0_MAT1/SWO
27 PIO0_8/MISO/CT16B0_MAT0
26 PIO2_2/DCD
25 PIO2_10
PIO2_9 24
002aae505
44 V
DD
LPC1343FBD48
PIO0_2/SSEL/CT16B0_CAP0 10
PIO2_7 11
PIO2_8 12
PIO2_1/DSR 13
PIO0_3/USB_VBUS 14
PIO0_4/SCL 15
PIO0_5/SDA 16
PIO1_9/CT16B1_MAT0 17
PIO2_4 18
USB_DM 19
USB_DP 20
PIO2_5 21
PIO0_6/USB_CONNECT/SCK 22
PIO0_7/CTS 23
Fig 2.
LPC1343 LQFP48 package
LPC1311_13_42_43_2
All information provided in this document is subject to legal disclaimers.
41 V
SS
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 6 May 2010
5 of 60
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