LPC11E3x
32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash; up
to 12 kB SRAM and 4 kB EEPROM; USART
Rev. 2 — 21 November 2013
Product data sheet
1. General description
The LPC11E3x are an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit
microcontroller applications, offering performance, low power, simple instruction set and
memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11E3x operate at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC11E3x includes up to 128 kB of flash memory, up to
12 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I
2
C-bus interface,
one RS-485/EIA-485 USART with support for synchronous mode and smart card
interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and up
to 54 general purpose I/O pins.
The I/O Handler is a software library-supported hardware engine that can be used to add
performance, connectivity and flexibility to system designs. It is available on the
LPC11E37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART,
I
2
C, and I
2
S with no or very low additional CPU load and can off-load the CPU by
performing processing-intensive functions like DMA transfers in hardware. Software
libraries for multiple I/O Handler applications are available on
http://www.LPCware.com.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Non Maskable Interrupt (NMI) input selectable from several input sources.
System tick timer.
Memory:
Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase
(256 byte) access.
4 kB on-chip EEPROM data memory; byte erasable and byte programmable;
on-chip API support.
12 kB SRAM data memory.
16 kB boot ROM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
ROM-based 32-bit integer division routines.
NXP Semiconductors
LPC11E3x
32-bit ARM Cortex-M0 microcontroller
Debug options:
Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan
Description Language).
Serial Wire Debug.
Digital peripherals:
Up to 54 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, and open-drain mode.
Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
Two GPIO grouped interrupt modules enable an interrupt based on a
programmable pattern of input states of a group of GPIO pins.
High-current source output driver (20 mA) on one pin.
High-current sink driver (20 mA) on true open-drain pins.
Four general purpose counter/timers with a total of up to 8 capture inputs and 13
match outputs.
Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDO).
Analog peripherals:
10-bit ADC with input multiplexing among eight pins.
Serial interfaces:
USART with fractional baud rate generation, internal FIFO, a full modem control
handshake interface, and support for RS-485/9-bit mode and synchronous mode.
USART supports an asynchronous smart card interface (ISO 7816-3).
Two SSP controllers with FIFO and multi-protocol capabilities.
I
2
C-bus interface supporting the full I
2
C-bus specification and Fast-mode Plus with
a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
I/O Handler for hardware emulation of serial interfaces and DMA; supported through
software libraries.(LPC11E37HFBD64/401 only.)
Clock generation:
Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).
12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as
a system clock.
Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable
frequency output.
PLL allows CPU operation up to the maximum CPU rate with the system oscillator
or the IRC as clock sources.
Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
Power control:
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, Power-down, and Deep power-down modes.
Power profiles residing in boot ROM provide optimized performance and minimized
power consumption for any given application through one simple function call.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Processor wake-up from Deep-sleep and Power-down modes via reset, selectable
GPIO pins, or the watchdog interrupt.
Processor wake-up from Deep power-down mode using one special function pin.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 21 November 2013
2 of 66
NXP Semiconductors
LPC11E3x
32-bit ARM Cortex-M0 microcontroller
Power-On Reset (POR).
Brownout detect with four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single 3.3 V power supply (1.8 V to 3.6 V).
Temperature range
40 C
to +85
C.
Available as LQFP64, LQFP48, and HVQFN33 packages.
3. Applications
Consumer peripherals
Medical
Handheld scanners
Industrial control
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC11E36FBD64/501
LPC11E36FHN33/501
LPC11E37FBD48/501
LPC11E37FBD64/501
LPC11E37HFBD64/401
LQFP64
HVQFN33
LQFP48
LQFP64
LQFP64
Description
plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7
7
0.85 mm
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
Version
n/a
SOT313-2
plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm SOT314-2
Type number
plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm SOT314-2
plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm SOT314-2
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 21 November 2013
3 of 66
NXP Semiconductors
LPC11E3x
32-bit ARM Cortex-M0 microcontroller
4.1 Ordering options
Table 2.
Ordering options
Total SRAM in kB
[1]
Type number
EEPROM in kB
SRAM0 in kB
SRAM2 in kB
SRAM1 in kB
ADC channels
I
2
C-bus FM+
Flash in kB
I/O Handler
LPC11E36FBD64/501
LPC11E36FHN33/501
LPC11E37FBD48/501
LPC11E37FBD64/501
LPC11E37HFBD64/401
[1]
[2]
96
96
128
128
128
4
4
4
4
4
8
8
8
8
8
2
2
2
2
2
2
[1]
2
[1]
2
[1]
2
[1]
2
[2]
12
12
12
12
10
no
no
no
no
1
1
1
1
1
1
1
1
1
2
2
2
2
2
8
8
8
8
8
54
28
40
54
54
yes 1
For general-purpose use.
For I/O Handler use only.
LPC11E3X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 21 November 2013
GPIO pins
4 of 66
USART
SSP
NXP Semiconductors
LPC11E3x
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
SWD, JTAG
XTALIN XTALOUT
RESET
LPC11E3x
TEST/DEBUG
INTERFACE
SYSTEM OSCILLATOR
IRC, WDO
BOD
POR
PLL0
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
CLKOUT
ARM
CORTEX-M0
system bus
slave
EEPROM
4 kB
FLASH
96/128 kB
slave
SRAM
10/12 kB
slave
ROM
16 kB
slave
GPIO ports 0/1
HIGH-SPEED
GPIO
I/O
HANDLER
(3)
master
AHB-LITE BUS
IOH_[20:0]
slave
AHB TO APB
BRIDGE
USART/
SMARTCARD INTERFACE
10-bit ADC
I
2
C-BUS
16-bit COUNTER/TIMER 0
SSP0
16-bit COUNTER/TIMER 1
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
SYSTEM CONTROL
WINDOWED WATCHDOG
TIMER
PMU
SSP1
IOCON
SCK0, SSEL0,
MISO0, MOSI0
SCK1, SSEL1,
MISO1, MOSI1
AD[7:0]
SCL, SDA
RXD
TXD
DCD, DSR
(1)
, RI
(1)
CTS, RTS, DTR
SCLK
CT16B0_MAT[2:0]
CT16B0_CAP[1:0]
(2)
CT16B1_MAT[1:0]
CT16B1_CAP[1:0]
(2)
CT32B0_MAT[3:0]
CT32B0_CAP[1:0]
(2)
CT32B1_MAT[3:0]
CT32B1_CAP[1:0]
(2)
GPIO pins
GPIO pins
GPIO pins
GPIO INTERRUPTS
GPIO GROUP0 INTERRUPTS
GPIO GROUP1 INTERRUPTS
002aah401
(1) Not available on HVQFN33 packages.
(2) CT16B0_CAP1, CT16B1_CAP1 available on LQFP64 packages only; CT32B0_CAP1 available LQFP48, and LQFP64
packages only; CT32B1_CAP1 available in LQFP64 packages only.
(3) LPC11E37HFBD64/401 only.
Fig 1.
LPC11E3X
Block diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 21 November 2013
5 of 66
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