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PR E LI MIN ARY

LM3S608 Microcontroller

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LM3S608 Microcontroller

Table of Contents

About This Document .................................................................................................................... 17

Audience ..............................................................................................................................................

About This Manual ................................................................................................................................

Related Documents ...............................................................................................................................

Documentation Conventions ..................................................................................................................

1.1

1.2

1.3

1.4

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

Architectural Overview ...................................................................................................... 19

Product Features ......................................................................................................................

Target Applications ....................................................................................................................

High-Level Block Diagram .........................................................................................................

Functional Overview ..................................................................................................................

ARM Cortex™-M3 .....................................................................................................................

Motor Control Peripherals ..........................................................................................................

Analog Peripherals ....................................................................................................................

Serial Communications Peripherals ............................................................................................

System Peripherals ...................................................................................................................

Memory Peripherals ..................................................................................................................

Additional Features ...................................................................................................................

Hardware Details ......................................................................................................................

Block Diagram ..........................................................................................................................

Functional Description ...............................................................................................................

Serial Wire and JTAG Debug .....................................................................................................

Embedded Trace Macrocell (ETM) .............................................................................................

Trace Port Interface Unit (TPIU) .................................................................................................

ROM Table ...............................................................................................................................

Memory Protection Unit (MPU) ...................................................................................................

Nested Vectored Interrupt Controller (NVIC) ................................................................................

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

ARM Cortex-M3 Processor Core ...................................................................................... 30

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.3

5.4

5.4.1

5.4.2

Memory Map ....................................................................................................................... 36

Interrupts ............................................................................................................................ 38

JTAG Interface .................................................................................................................... 40

Block Diagram ..........................................................................................................................

Functional Description ...............................................................................................................

JTAG Interface Pins ..................................................................................................................

JTAG TAP Controller .................................................................................................................

Shift Registers ..........................................................................................................................

Operational Considerations ........................................................................................................

Initialization and Configuration ...................................................................................................

Register Descriptions ................................................................................................................

Instruction Register (IR) .............................................................................................................

Data Registers ..........................................................................................................................

6.1

6.1.1

6.1.2

System Control ................................................................................................................... 50

Functional Description ............................................................................................................... 50

Device Identification .................................................................................................................. 50

Reset Control ............................................................................................................................ 50

October 01, 2007

Preliminary

Table of Contents

6.1.3

6.1.4

6.1.5

6.2

6.3

6.4

Power Control ...........................................................................................................................

Clock Control ............................................................................................................................

System Control .........................................................................................................................

Initialization and Configuration ...................................................................................................

Register Map ............................................................................................................................

Register Descriptions ................................................................................................................

7.1

7.2

7.2.1

7.2.2

7.3

7.3.1

7.3.2

7.4

7.5

7.6

Internal Memory ............................................................................................................... 108

Block Diagram ........................................................................................................................ 108

Functional Description ............................................................................................................. 108

SRAM Memory ........................................................................................................................ 108

Flash Memory ......................................................................................................................... 109

Flash Memory Initialization and Configuration ........................................................................... 111

Changing Flash Protection Bits ................................................................................................ 111

Flash Programming ................................................................................................................. 112

Register Map .......................................................................................................................... 112

Flash Register Descriptions (Flash Control Offset) ..................................................................... 113

Flash Register Descriptions (System Control Offset) .................................................................. 120

8.1

8.1.1

8.1.2

8.1.3

8.1.4

8.1.5

8.2

8.3

8.4

General-Purpose Input/Outputs (GPIOs) ....................................................................... 124

Functional Description ............................................................................................................. 124

Data Control ........................................................................................................................... 125

Interrupt Control ...................................................................................................................... 126

Mode Control .......................................................................................................................... 127

Pad Control ............................................................................................................................. 127

Identification ........................................................................................................................... 127

Initialization and Configuration ................................................................................................. 127

Register Map .......................................................................................................................... 128

Register Descriptions .............................................................................................................. 130

9.1

9.2

9.2.1

9.2.2

9.2.3

9.3

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9.4

9.5

General-Purpose Timers ................................................................................................. 162

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

GPTM Reset Conditions ..........................................................................................................

32-Bit Timer Operating Modes ..................................................................................................

16-Bit Timer Operating Modes ..................................................................................................

Initialization and Configuration .................................................................................................

32-Bit One-Shot/Periodic Timer Mode .......................................................................................

32-Bit Real-Time Clock (RTC) Mode .........................................................................................

16-Bit One-Shot/Periodic Timer Mode .......................................................................................

16-Bit Input Edge Count Mode .................................................................................................

16-Bit Input Edge Timing Mode ................................................................................................

16-Bit PWM Mode ...................................................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Initialization and Configuration .................................................................................................

Register Map ..........................................................................................................................

163

165

169

170

171

172

173

198

199

10.1

10.2

10.3

10.4

Watchdog Timer ............................................................................................................... 198

Preliminary

October 01, 2007

LM3S608 Microcontroller

10.5

Register Descriptions .............................................................................................................. 200

11.1

11.2

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

11.3

11.3.1

11.3.2

11.4

11.5

Analog-to-Digital Converter (ADC) ................................................................................. 221

Block Diagram ........................................................................................................................ 222

Functional Description ............................................................................................................. 222

Sample Sequencers ................................................................................................................ 222

Module Control ........................................................................................................................ 223

Hardware Sample Averaging Circuit ......................................................................................... 224

Analog-to-Digital Converter ...................................................................................................... 224

Test Modes ............................................................................................................................. 224

Internal Temperature Sensor .................................................................................................... 224

Initialization and Configuration ................................................................................................. 225

Module Initialization ................................................................................................................. 225

Sample Sequencer Configuration ............................................................................................. 225

Register Map .......................................................................................................................... 226

Register Descriptions .............................................................................................................. 227

12.1

12.2

12.2.1

12.2.2

12.2.3

12.2.4

12.2.5

12.2.6

12.3

12.4

12.5

Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 254

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Transmit/Receive Logic ...........................................................................................................

Baud-Rate Generation .............................................................................................................

Data Transmission ..................................................................................................................

FIFO Operation .......................................................................................................................

Interrupts ................................................................................................................................

Loopback Operation ................................................................................................................

Initialization and Configuration .................................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Bit Rate Generation .................................................................................................................

FIFO Operation .......................................................................................................................

Interrupts ................................................................................................................................

Frame Formats .......................................................................................................................

Initialization and Configuration .................................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

C Bus Functional Overview ....................................................................................................

Available Speed Modes ...........................................................................................................

Interrupts ................................................................................................................................

Loopback Operation ................................................................................................................

Command Sequence Flow Charts ............................................................................................

Initialization and Configuration .................................................................................................

C Register Map .....................................................................................................................

255

256

257

258

259

260

292

293

294

301

302

303

329

330

332

333

334

340

341

13.1

13.2

13.2.1

13.2.2

13.2.3

13.2.4

13.3

13.4

13.5

Synchronous Serial Interface (SSI) ................................................................................ 292

14.1

14.2

14.2.1

14.2.2

14.2.3

14.2.4

14.2.5

14.3

14.4

Inter-Integrated Circuit (I

C) Interface ............................................................................ 329

October 01, 2007

Preliminary

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器件捷径: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

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