P RE L I M I NA R Y
LM3S601 Microcontroller
D A TA SH EET
DS -LM3S 601- 01
C opyr ight © 2006 Lumi nary Micro , Inc.
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2
Preliminary
October 8, 2006
LM3S601 Data Sheet
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 18
About This Document..................................................................................................................... 19
Audience........................................................................................................................................................... 19
About This Manual............................................................................................................................................ 19
Related Documents .......................................................................................................................................... 19
Documentation Conventions............................................................................................................................. 19
1.
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.5
Architectural Overview ....................................................................................................... 22
Product Features ................................................................................................................................. 22
Target Applications .............................................................................................................................. 26
High-Level Block Diagram ................................................................................................................... 27
Functional Overview ............................................................................................................................ 28
ARM Cortex™-M3 ............................................................................................................................... 28
Motor Control Peripherals .................................................................................................................... 28
Analog Peripherals .............................................................................................................................. 29
Serial Communications Peripherals..................................................................................................... 29
System Peripherals.............................................................................................................................. 30
Memory Peripherals............................................................................................................................. 31
Additional Features .............................................................................................................................. 31
Hardware Details ................................................................................................................................. 32
System Block Diagram ........................................................................................................................ 33
2.
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core........................................................................................ 34
Block Diagram ..................................................................................................................................... 35
Functional Description ......................................................................................................................... 35
Serial Wire and JTAG Debug .............................................................................................................. 35
Embedded Trace Macrocell (ETM) ...................................................................................................... 36
Trace Port Interface Unit (TPIU) .......................................................................................................... 36
ROM Table .......................................................................................................................................... 36
Memory Protection Unit (MPU) ............................................................................................................ 36
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 36
3.
4.
5.
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ........................................................................................................................ 37
Interrupts ............................................................................................................................. 39
JTAG Interface .................................................................................................................... 42
Block Diagram ..................................................................................................................................... 43
Functional Description ......................................................................................................................... 43
JTAG Interface Pins............................................................................................................................. 44
JTAG TAP Controller ........................................................................................................................... 45
Shift Registers ..................................................................................................................................... 46
Operational Considerations ................................................................................................................. 46
Initialization and Configuration............................................................................................................. 47
Register Descriptions........................................................................................................................... 48
Instruction Register (IR) ....................................................................................................................... 48
Data Registers ..................................................................................................................................... 50
October 8, 2006
Preliminary
3
Table of Contents
6.
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
System Control.................................................................................................................... 52
Functional Description ......................................................................................................................... 52
Device Identification............................................................................................................................. 52
Reset Control ....................................................................................................................................... 52
Power Control ...................................................................................................................................... 55
Clock Control ....................................................................................................................................... 55
System Control .................................................................................................................................... 57
Initialization and Configuration............................................................................................................. 58
Register Map ....................................................................................................................................... 58
Register Descriptions........................................................................................................................... 59
7.
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
Internal Memory .................................................................................................................. 95
Block Diagram ..................................................................................................................................... 95
Functional Description ......................................................................................................................... 95
SRAM Memory .................................................................................................................................... 95
Flash Memory ...................................................................................................................................... 96
Initialization and Configuration............................................................................................................. 97
Changing Flash Protection Bits ........................................................................................................... 97
Flash Programming ............................................................................................................................. 98
Register Map ....................................................................................................................................... 98
Register Descriptions........................................................................................................................... 99
8.
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.4
8.5
General-Purpose Input/Outputs (GPIOs) ........................................................................ 109
Block Diagram ................................................................................................................................... 110
Functional Description ....................................................................................................................... 110
Data Register Operation .................................................................................................................... 111
Data Direction .................................................................................................................................... 112
Interrupt Operation............................................................................................................................. 112
Mode Control ..................................................................................................................................... 113
Pad Configuration .............................................................................................................................. 113
Identification....................................................................................................................................... 113
Initialization and Configuration........................................................................................................... 113
Register Map ..................................................................................................................................... 115
Register Descriptions......................................................................................................................... 116
9.
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers .................................................................................................. 147
Block Diagram ................................................................................................................................... 148
Functional Description ....................................................................................................................... 148
GPTM Reset Conditions .................................................................................................................... 148
32-Bit Timer Operating Modes........................................................................................................... 148
16-Bit Timer Operating Modes........................................................................................................... 150
Initialization and Configuration........................................................................................................... 154
32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 154
32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 155
16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 155
16-Bit Input Edge Count Mode .......................................................................................................... 155
16-Bit Input Edge Timing Mode ......................................................................................................... 156
16-Bit PWM Mode.............................................................................................................................. 156
Register Map ..................................................................................................................................... 157
Register Descriptions......................................................................................................................... 158
4
Preliminary
October 8, 2006
LM3S601 Data Sheet
10.
10.1
10.2
10.3
10.4
10.5
Watchdog Timer ................................................................................................................ 179
Block Diagram ................................................................................................................................... 179
Functional Description ....................................................................................................................... 180
Initialization and Configuration........................................................................................................... 180
Register Map ..................................................................................................................................... 180
Register Descriptions......................................................................................................................... 181
11.
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.4
11.5
Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 202
Block Diagram ................................................................................................................................... 203
Functional Description ....................................................................................................................... 203
Transmit/Receive Logic ..................................................................................................................... 203
Baud-Rate Generation ....................................................................................................................... 204
Data Transmission ............................................................................................................................. 205
FIFO Operation .................................................................................................................................. 205
Interrupts............................................................................................................................................ 205
Loopback Operation .......................................................................................................................... 206
Initialization and Configuration........................................................................................................... 206
Register Map ..................................................................................................................................... 207
Register Descriptions......................................................................................................................... 208
12.
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.3
12.4
12.5
Synchronous Serial Interface (SSI) ................................................................................. 238
Block Diagram ................................................................................................................................... 238
Functional Description ....................................................................................................................... 239
Bit Rate Generation ........................................................................................................................... 239
FIFO Operation .................................................................................................................................. 239
Interrupts............................................................................................................................................ 239
Frame Formats .................................................................................................................................. 240
Initialization and Configuration........................................................................................................... 247
Register Map ..................................................................................................................................... 248
Register Descriptions......................................................................................................................... 249
13.
13.1
13.2
13.2.1
13.2.2
13.3
13.4
13.5
13.6
Inter-Integrated Circuit (I2C) Interface ............................................................................ 273
Block Diagram ................................................................................................................................... 273
Functional Description ....................................................................................................................... 273
I
2
C Bus Functional Overview ............................................................................................................. 274
Available Speed Modes ..................................................................................................................... 281
Initialization and Configuration........................................................................................................... 282
Register Map ..................................................................................................................................... 283
Register Descriptions (I2C Master).................................................................................................... 283
Register Descriptions (I2C Slave)...................................................................................................... 297
14.
14.1
14.2
14.2.1
14.3
14.4
14.5
Analog Comparators......................................................................................................... 305
Block Diagram ................................................................................................................................... 305
Functional Description ....................................................................................................................... 306
Internal Reference Programming....................................................................................................... 307
Initialization and Configuration........................................................................................................... 308
Register Map ..................................................................................................................................... 309
Register Descriptions......................................................................................................................... 309
15.
Pulse Width Modulator (PWM) ......................................................................................... 317
15.1
Block Diagram ................................................................................................................................... 317
15.2
Functional Description ....................................................................................................................... 317
15.2.1 PWM Timer ........................................................................................................................................ 317
October 8, 2006
Preliminary
5
NXP MCU
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