PR E LI MIN ARY
LM3S3748 Microcontroller
DATA SHEE T
DS-LM3S3 748-2 83 0
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2 00 7-2 00 8 L umin ary Mi cro , In c.
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Preliminary
April 08, 2008
LM3S3748 Microcontroller
Table of Contents
About This Document .................................................................................................................... 23
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
23
23
23
23
26
33
34
35
35
36
37
37
39
39
40
41
43
43
44
44
44
44
44
45
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview ...................................................................................................... 26
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Analog Peripherals ....................................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 42
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 48
Interrupts ............................................................................................................................ 51
JTAG Interface .................................................................................................................... 54
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
55
55
56
57
58
58
61
61
61
63
6
6.1
6.1.1
6.1.2
System Control ................................................................................................................... 66
Functional Description ............................................................................................................... 66
Device Identification .................................................................................................................. 66
Reset Control ............................................................................................................................ 66
April 08, 2008
Preliminary
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Table of Contents
6.1.3
6.1.4
6.1.5
6.1.6
6.2
6.3
6.4
Non-Maskable Interrupt .............................................................................................................
Power Control ...........................................................................................................................
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Register Access Timing ...........................................................................................................
Clock Source ..........................................................................................................................
Battery Management ...............................................................................................................
Real-Time Clock ......................................................................................................................
Non-Volatile Memory ...............................................................................................................
Power Control .........................................................................................................................
Interrupts and Status ...............................................................................................................
Initialization and Configuration .................................................................................................
Initialization .............................................................................................................................
RTC Match Functionality (No Hibernation) ................................................................................
RTC Match/Wake-Up from Hibernation .....................................................................................
External Wake-Up from Hibernation ..........................................................................................
RTC/External Wake-Up from Hibernation ..................................................................................
Register Reset ........................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
69
69
69
73
74
75
76
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.4
7.5
Hibernation Module .......................................................................................................... 137
138
138
138
139
141
142
142
142
143
143
143
144
144
144
144
144
145
146
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
8.4
8.5
8.6
8.7
Internal Memory ............................................................................................................... 160
Block Diagram ........................................................................................................................ 160
Functional Description ............................................................................................................. 160
SRAM Memory ........................................................................................................................ 160
ROM Memory ......................................................................................................................... 161
Flash Memory ......................................................................................................................... 161
Flash Memory Initialization and Configuration ........................................................................... 162
Flash Programming ................................................................................................................. 162
Nonvolatile Register Programming ........................................................................................... 163
Register Map .......................................................................................................................... 164
ROM Register Descriptions (System Control Offset) .................................................................. 165
Flash Register Descriptions (Flash Control Offset) ..................................................................... 166
Flash Register Descriptions (System Control Offset) .................................................................. 173
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
Micro Direct Memory Access (μDMA) ............................................................................ 189
Block Diagram ........................................................................................................................ 190
Functional Description ............................................................................................................. 190
Channel Assigments ................................................................................................................ 191
Priority .................................................................................................................................... 191
Arbitration Size ........................................................................................................................ 191
Request Types ........................................................................................................................ 192
Channel Configuration ............................................................................................................. 192
Transfer Modes ....................................................................................................................... 194
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LM3S3748 Microcontroller
9.2.7
9.2.8
9.2.9
9.2.10
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.4
9.5
9.6
Transfer Size and Increment ....................................................................................................
Peripheral Interface .................................................................................................................
Software Request ....................................................................................................................
Interrupts and Errors ................................................................................................................
Initialization and Configuration .................................................................................................
Module Initialization .................................................................................................................
Configuring a Memory-to-Memory Transfer ...............................................................................
Configuring a Peripheral for Simple Transmit ............................................................................
Configuring a Peripheral for Ping-Pong Receive ........................................................................
Register Map ..........................................................................................................................
μDMA Channel Control Structure .............................................................................................
μDMA Register Descriptions ....................................................................................................
202
202
202
203
203
203
203
205
206
209
210
216
10
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
10.1.6
10.2
10.3
10.4
General-Purpose Input/Outputs (GPIOs) ....................................................................... 250
Functional Description ............................................................................................................. 250
Data Control ........................................................................................................................... 252
Interrupt Control ...................................................................................................................... 253
Mode Control .......................................................................................................................... 254
Commit Control ....................................................................................................................... 254
Pad Control ............................................................................................................................. 254
Identification ........................................................................................................................... 255
Initialization and Configuration ................................................................................................. 255
Register Map .......................................................................................................................... 256
Register Descriptions .............................................................................................................. 258
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.4
11.5
General-Purpose Timers ................................................................................................. 297
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
297
298
299
299
300
304
304
305
305
306
306
307
307
308
331
331
332
332
333
12
12.1
12.2
12.3
12.4
12.5
Watchdog Timer ............................................................................................................... 331
13
13.1
13.2
Analog-to-Digital Converter (ADC) ................................................................................. 354
Block Diagram ........................................................................................................................ 355
Functional Description ............................................................................................................. 355
April 08, 2008
Preliminary
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FPGA/CPLD
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