P REL I MIN AR Y
LM3S328 Microcontroller
D A TA S H E E T
DS-LM3S32 8-03
Co pyrigh t © 200 7 Lumin ary Micro, In c.
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2
Preliminary
April 27, 2007
LM3S328 Data Sheet
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 15
About This Document..................................................................................................................... 17
Audience........................................................................................................................................................... 17
About This Manual............................................................................................................................................ 17
Related Documents .......................................................................................................................................... 17
Documentation Conventions............................................................................................................................. 17
1.
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.5
Architectural Overview ....................................................................................................... 20
Product Features ................................................................................................................................. 20
Target Applications .............................................................................................................................. 23
High-Level Block Diagram ................................................................................................................... 24
Functional Overview ............................................................................................................................ 25
ARM Cortex™-M3 ............................................................................................................................... 25
Motor Control Peripherals .................................................................................................................... 25
Analog Peripherals .............................................................................................................................. 25
Serial Communications Peripherals..................................................................................................... 26
System Peripherals.............................................................................................................................. 27
Memory Peripherals............................................................................................................................. 27
Additional Features .............................................................................................................................. 28
Hardware Details ................................................................................................................................. 28
System Block Diagram ........................................................................................................................ 30
2.
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core........................................................................................ 31
Block Diagram ..................................................................................................................................... 32
Functional Description ......................................................................................................................... 32
Serial Wire and JTAG Debug .............................................................................................................. 32
Embedded Trace Macrocell (ETM) ...................................................................................................... 33
Trace Port Interface Unit (TPIU) .......................................................................................................... 33
ROM Table .......................................................................................................................................... 33
Memory Protection Unit (MPU) ............................................................................................................ 33
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 33
3.
4.
5.
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ........................................................................................................................ 39
Interrupts ............................................................................................................................. 41
JTAG Interface .................................................................................................................... 44
Block Diagram ..................................................................................................................................... 45
Functional Description ......................................................................................................................... 45
JTAG Interface Pins............................................................................................................................. 46
JTAG TAP Controller ........................................................................................................................... 47
Shift Registers ..................................................................................................................................... 48
Operational Considerations ................................................................................................................. 48
Initialization and Configuration............................................................................................................. 49
Register Descriptions........................................................................................................................... 50
Instruction Register (IR) ....................................................................................................................... 50
Data Registers ..................................................................................................................................... 52
6.
6.1
6.1.1
System Control.................................................................................................................... 54
Functional Description ......................................................................................................................... 54
Device Identification............................................................................................................................. 54
April 27, 2007
Preliminary
3
Table of Contents
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Reset Control ....................................................................................................................................... 54
Power Control ...................................................................................................................................... 57
Clock Control ....................................................................................................................................... 57
System Control .................................................................................................................................... 59
Initialization and Configuration............................................................................................................. 60
Register Map ....................................................................................................................................... 60
Register Descriptions........................................................................................................................... 61
7.
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
Internal Memory .................................................................................................................. 95
Block Diagram ..................................................................................................................................... 95
Functional Description ......................................................................................................................... 95
SRAM Memory .................................................................................................................................... 95
Flash Memory ...................................................................................................................................... 96
Initialization and Configuration............................................................................................................. 98
Changing Flash Protection Bits ........................................................................................................... 98
Flash Programming ............................................................................................................................. 99
Register Map ....................................................................................................................................... 99
Register Descriptions......................................................................................................................... 100
8.
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.4
8.5
General-Purpose Input/Outputs (GPIOs) ........................................................................ 112
Block Diagram ................................................................................................................................... 113
Functional Description ....................................................................................................................... 113
Data Register Operation .................................................................................................................... 114
Data Direction .................................................................................................................................... 115
Interrupt Operation............................................................................................................................. 115
Mode Control ..................................................................................................................................... 116
Pad Configuration .............................................................................................................................. 116
Identification....................................................................................................................................... 116
Initialization and Configuration........................................................................................................... 116
Register Map ..................................................................................................................................... 118
Register Descriptions......................................................................................................................... 119
9.
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers .................................................................................................. 150
Block Diagram ................................................................................................................................... 151
Functional Description ....................................................................................................................... 151
GPTM Reset Conditions .................................................................................................................... 151
32-Bit Timer Operating Modes........................................................................................................... 151
16-Bit Timer Operating Modes........................................................................................................... 153
Initialization and Configuration........................................................................................................... 157
32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 157
32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 158
16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 158
16-Bit Input Edge Count Mode .......................................................................................................... 158
16-Bit Input Edge Timing Mode ......................................................................................................... 159
16-Bit PWM Mode.............................................................................................................................. 159
Register Map ..................................................................................................................................... 160
Register Descriptions......................................................................................................................... 161
10.
10.1
10.2
10.3
Watchdog Timer ................................................................................................................ 182
Block Diagram ................................................................................................................................... 182
Functional Description ....................................................................................................................... 183
Initialization and Configuration........................................................................................................... 183
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Preliminary
April 27, 2007
LM3S328 Data Sheet
10.4
10.5
Register Map ..................................................................................................................................... 183
Register Descriptions......................................................................................................................... 184
11.
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.3.1
11.3.2
11.4
11.5
Analog-to-Digital Converter (ADC) .................................................................................. 205
Block Diagram ................................................................................................................................... 205
Functional Description ....................................................................................................................... 206
Sample Sequencers .......................................................................................................................... 206
Module Control .................................................................................................................................. 207
Hardware Sample Averaging Circuit.................................................................................................. 207
Analog-to-Digital Converter ............................................................................................................... 207
Test Modes ........................................................................................................................................ 207
Internal Temperature Sensor ............................................................................................................. 208
Initialization and Configuration........................................................................................................... 208
Module Initialization ........................................................................................................................... 208
Sample Sequencer Configuration ...................................................................................................... 208
Register Map ..................................................................................................................................... 209
Register Descriptions......................................................................................................................... 210
12.
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.3
12.4
12.5
Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 235
Block Diagram ................................................................................................................................... 236
Functional Description ....................................................................................................................... 236
Transmit/Receive Logic ..................................................................................................................... 236
Baud-Rate Generation ....................................................................................................................... 237
Data Transmission ............................................................................................................................. 238
FIFO Operation .................................................................................................................................. 238
Interrupts............................................................................................................................................ 238
Loopback Operation .......................................................................................................................... 239
Initialization and Configuration........................................................................................................... 239
Register Map ..................................................................................................................................... 240
Register Descriptions......................................................................................................................... 241
13.
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.4
13.5
Synchronous Serial Interface (SSI) ................................................................................. 271
Block Diagram ................................................................................................................................... 271
Functional Description ....................................................................................................................... 272
Bit Rate Generation ........................................................................................................................... 272
FIFO Operation .................................................................................................................................. 272
Interrupts............................................................................................................................................ 272
Frame Formats .................................................................................................................................. 273
Initialization and Configuration........................................................................................................... 280
Register Map ..................................................................................................................................... 281
Register Descriptions......................................................................................................................... 282
14.
14.1
14.2
14.2.1
14.2.2
14.3
14.4
14.5
14.6
Inter-Integrated Circuit (I2C) Interface ............................................................................ 306
Block Diagram ................................................................................................................................... 306
Functional Description ....................................................................................................................... 306
I
2
C Bus Functional Overview ............................................................................................................. 307
Available Speed Modes ..................................................................................................................... 316
Initialization and Configuration........................................................................................................... 317
Register Map ..................................................................................................................................... 318
Register Descriptions (I2C Master).................................................................................................... 318
Register Descriptions (I2C Slave)...................................................................................................... 332
April 27, 2007
Preliminary
5
FPGA/CPLD
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