P RE L I M I NA R Y
LM3S328 Microcontroller
D A TA SH EET
DS -LM3S 328- 01
C opyr ight © 2006 Lumi nary Micro , Inc.
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2
Preliminary
October 8, 2006
LM3S328 Data Sheet
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 15
About This Document..................................................................................................................... 16
Audience........................................................................................................................................................... 16
About This Manual............................................................................................................................................ 16
Related Documents .......................................................................................................................................... 16
Documentation Conventions............................................................................................................................. 16
1.
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.5
Architectural Overview ....................................................................................................... 19
Product Features ................................................................................................................................. 19
Target Applications .............................................................................................................................. 22
High-Level Block Diagram ................................................................................................................... 23
Functional Overview ............................................................................................................................ 24
ARM Cortex™-M3 ............................................................................................................................... 24
Motor Control Peripherals .................................................................................................................... 24
Analog Peripherals .............................................................................................................................. 24
Serial Communications Peripherals..................................................................................................... 25
System Peripherals.............................................................................................................................. 26
Memory Peripherals............................................................................................................................. 26
Additional Features .............................................................................................................................. 27
Hardware Details ................................................................................................................................. 27
System Block Diagram ........................................................................................................................ 29
2.
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core........................................................................................ 30
Block Diagram ..................................................................................................................................... 31
Functional Description ......................................................................................................................... 31
Serial Wire and JTAG Debug .............................................................................................................. 31
Embedded Trace Macrocell (ETM) ...................................................................................................... 32
Trace Port Interface Unit (TPIU) .......................................................................................................... 32
ROM Table .......................................................................................................................................... 32
Memory Protection Unit (MPU) ............................................................................................................ 32
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 32
3.
4.
5.
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ........................................................................................................................ 33
Interrupts ............................................................................................................................. 35
JTAG Interface .................................................................................................................... 38
Block Diagram ..................................................................................................................................... 39
Functional Description ......................................................................................................................... 39
JTAG Interface Pins............................................................................................................................. 40
JTAG TAP Controller ........................................................................................................................... 41
Shift Registers ..................................................................................................................................... 42
Operational Considerations ................................................................................................................. 42
Initialization and Configuration............................................................................................................. 43
Register Descriptions........................................................................................................................... 44
Instruction Register (IR) ....................................................................................................................... 44
Data Registers ..................................................................................................................................... 46
6.
6.1
6.1.1
System Control.................................................................................................................... 48
Functional Description ......................................................................................................................... 48
Device Identification............................................................................................................................. 48
October 8, 2006
Preliminary
3
Table of Contents
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Reset Control ....................................................................................................................................... 48
Power Control ...................................................................................................................................... 51
Clock Control ....................................................................................................................................... 51
System Control .................................................................................................................................... 53
Initialization and Configuration............................................................................................................. 54
Register Map ....................................................................................................................................... 54
Register Descriptions........................................................................................................................... 55
7.
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
Internal Memory .................................................................................................................. 89
Block Diagram ..................................................................................................................................... 89
Functional Description ......................................................................................................................... 89
SRAM Memory .................................................................................................................................... 89
Flash Memory ...................................................................................................................................... 90
Initialization and Configuration............................................................................................................. 91
Changing Flash Protection Bits ........................................................................................................... 91
Flash Programming ............................................................................................................................. 92
Register Map ....................................................................................................................................... 92
Register Descriptions........................................................................................................................... 93
8.
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.4
8.5
General-Purpose Input/Outputs (GPIOs) ........................................................................ 103
Block Diagram ................................................................................................................................... 104
Functional Description ....................................................................................................................... 104
Data Register Operation .................................................................................................................... 105
Data Direction .................................................................................................................................... 106
Interrupt Operation............................................................................................................................. 106
Mode Control ..................................................................................................................................... 107
Pad Configuration .............................................................................................................................. 107
Identification....................................................................................................................................... 107
Initialization and Configuration........................................................................................................... 107
Register Map ..................................................................................................................................... 109
Register Descriptions......................................................................................................................... 110
9.
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers .................................................................................................. 141
Block Diagram ................................................................................................................................... 142
Functional Description ....................................................................................................................... 142
GPTM Reset Conditions .................................................................................................................... 142
32-Bit Timer Operating Modes........................................................................................................... 142
16-Bit Timer Operating Modes........................................................................................................... 144
Initialization and Configuration........................................................................................................... 148
32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 148
32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 149
16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 149
16-Bit Input Edge Count Mode .......................................................................................................... 149
16-Bit Input Edge Timing Mode ......................................................................................................... 150
16-Bit PWM Mode.............................................................................................................................. 150
Register Map ..................................................................................................................................... 151
Register Descriptions......................................................................................................................... 152
10.
10.1
10.2
10.3
10.4
Watchdog Timer ................................................................................................................ 173
Block Diagram ................................................................................................................................... 173
Functional Description ....................................................................................................................... 174
Initialization and Configuration........................................................................................................... 174
Register Map ..................................................................................................................................... 174
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Preliminary
October 8, 2006
LM3S328 Data Sheet
10.5
Register Descriptions......................................................................................................................... 175
11.
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.3.1
11.3.2
11.4
11.5
Analog-to-Digital Converter (ADC) .................................................................................. 196
Block Diagram ................................................................................................................................... 196
Functional Description ....................................................................................................................... 197
Sample Sequencers .......................................................................................................................... 197
Module Control .................................................................................................................................. 198
Hardware Sample Averaging Circuit.................................................................................................. 198
Analog-to-Digital Converter ............................................................................................................... 198
Test Modes ........................................................................................................................................ 198
Internal Temperature Sensor ............................................................................................................. 199
Initialization and Configuration........................................................................................................... 199
Module Initialization ........................................................................................................................... 199
Sample Sequencer Configuration ...................................................................................................... 199
Register Map ..................................................................................................................................... 200
Register Descriptions......................................................................................................................... 201
12.
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.3
12.4
12.5
Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 226
Block Diagram ................................................................................................................................... 227
Functional Description ....................................................................................................................... 227
Transmit/Receive Logic ..................................................................................................................... 227
Baud-Rate Generation ....................................................................................................................... 228
Data Transmission ............................................................................................................................. 229
FIFO Operation .................................................................................................................................. 229
Interrupts............................................................................................................................................ 229
Loopback Operation .......................................................................................................................... 230
Initialization and Configuration........................................................................................................... 230
Register Map ..................................................................................................................................... 231
Register Descriptions......................................................................................................................... 232
13.
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.4
13.5
Synchronous Serial Interface (SSI) ................................................................................. 262
Block Diagram ................................................................................................................................... 262
Functional Description ....................................................................................................................... 263
Bit Rate Generation ........................................................................................................................... 263
FIFO Operation .................................................................................................................................. 263
Interrupts............................................................................................................................................ 263
Frame Formats .................................................................................................................................. 264
Initialization and Configuration........................................................................................................... 271
Register Map ..................................................................................................................................... 272
Register Descriptions......................................................................................................................... 273
14.
14.1
14.2
14.2.1
14.2.2
14.3
14.4
14.5
14.6
Inter-Integrated Circuit (I2C) Interface ............................................................................ 297
Block Diagram ................................................................................................................................... 297
Functional Description ....................................................................................................................... 297
I
2
C Bus Functional Overview ............................................................................................................. 298
Available Speed Modes ..................................................................................................................... 305
Initialization and Configuration........................................................................................................... 306
Register Map ..................................................................................................................................... 306
Register Descriptions (I2C Master).................................................................................................... 307
Register Descriptions (I2C Slave)...................................................................................................... 321
October 8, 2006
Preliminary
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