P RE L I M I NA R Y
LM3S310 Microcontroller
D A TA SH EET
DS -LM3S 310- 02
C opyr ight © 2006 Lumi nary Micro , Inc.
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2
Preliminary
October 6, 2006
LM3S310 Data Sheet
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 15
About This Document..................................................................................................................... 16
Audience........................................................................................................................................................... 16
About This Manual............................................................................................................................................ 16
Related Documents .......................................................................................................................................... 16
Documentation Conventions............................................................................................................................. 16
1.
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.5
Architectural Overview ....................................................................................................... 19
Product Features ................................................................................................................................. 19
Target Applications .............................................................................................................................. 22
High-Level Block Diagram ................................................................................................................... 23
Functional Overview ............................................................................................................................ 24
ARM Cortex™-M3 ............................................................................................................................... 24
Motor Control Peripherals .................................................................................................................... 24
Analog Peripherals .............................................................................................................................. 25
Serial Communications Peripherals..................................................................................................... 25
System Peripherals.............................................................................................................................. 26
Memory Peripherals............................................................................................................................. 26
Additional Features .............................................................................................................................. 27
Hardware Details ................................................................................................................................. 27
System Block Diagram ........................................................................................................................ 29
2.
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core........................................................................................ 30
Block Diagram ..................................................................................................................................... 31
Functional Description ......................................................................................................................... 31
Serial Wire and JTAG Debug .............................................................................................................. 31
Embedded Trace Macrocell (ETM) ...................................................................................................... 32
Trace Port Interface Unit (TPIU) .......................................................................................................... 32
ROM Table .......................................................................................................................................... 32
Memory Protection Unit (MPU) ............................................................................................................ 32
Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 32
3.
4.
5.
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ........................................................................................................................ 33
Interrupts ............................................................................................................................. 35
JTAG Interface .................................................................................................................... 38
Block Diagram ..................................................................................................................................... 39
Functional Description ......................................................................................................................... 39
JTAG Interface Pins............................................................................................................................. 40
JTAG TAP Controller ........................................................................................................................... 41
Shift Registers ..................................................................................................................................... 42
Operational Considerations ................................................................................................................. 42
Initialization and Configuration............................................................................................................. 43
Register Descriptions........................................................................................................................... 44
Instruction Register (IR) ....................................................................................................................... 44
Data Registers ..................................................................................................................................... 46
6.
6.1
6.1.1
System Control.................................................................................................................... 48
Functional Description ......................................................................................................................... 48
Device Identification............................................................................................................................. 48
October 6, 2006
Preliminary
3
Table of Contents
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Reset Control ....................................................................................................................................... 48
Power Control ...................................................................................................................................... 51
Clock Control ....................................................................................................................................... 51
System Control .................................................................................................................................... 53
Initialization and Configuration............................................................................................................. 54
Register Map ....................................................................................................................................... 54
Register Descriptions........................................................................................................................... 55
7.
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
Internal Memory .................................................................................................................. 90
Block Diagram ..................................................................................................................................... 90
Functional Description ......................................................................................................................... 90
SRAM Memory .................................................................................................................................... 90
Flash Memory ...................................................................................................................................... 91
Initialization and Configuration............................................................................................................. 92
Changing Flash Protection Bits ........................................................................................................... 92
Flash Programming ............................................................................................................................. 93
Register Map ....................................................................................................................................... 93
Register Descriptions........................................................................................................................... 94
8.
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.4
8.5
General-Purpose Input/Outputs (GPIOs) ........................................................................ 104
Block Diagram ................................................................................................................................... 105
Functional Description ....................................................................................................................... 105
Data Register Operation .................................................................................................................... 106
Data Direction .................................................................................................................................... 107
Interrupt Operation............................................................................................................................. 107
Mode Control ..................................................................................................................................... 108
Pad Configuration .............................................................................................................................. 108
Identification....................................................................................................................................... 108
Initialization and Configuration........................................................................................................... 108
Register Map ..................................................................................................................................... 110
Register Descriptions......................................................................................................................... 111
9.
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers .................................................................................................. 142
Block Diagram ................................................................................................................................... 143
Functional Description ....................................................................................................................... 143
GPTM Reset Conditions .................................................................................................................... 143
32-Bit Timer Operating Modes........................................................................................................... 143
16-Bit Timer Operating Modes........................................................................................................... 145
Initialization and Configuration........................................................................................................... 149
32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 149
32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 150
16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 150
16-Bit Input Edge Count Mode .......................................................................................................... 150
16-Bit Input Edge Timing Mode ......................................................................................................... 151
16-Bit PWM Mode.............................................................................................................................. 151
Register Map ..................................................................................................................................... 152
Register Descriptions......................................................................................................................... 153
10.
10.1
10.2
10.3
10.4
Watchdog Timer ................................................................................................................ 174
Block Diagram ................................................................................................................................... 174
Functional Description ....................................................................................................................... 175
Initialization and Configuration........................................................................................................... 175
Register Map ..................................................................................................................................... 175
4
Preliminary
October 6, 2006
LM3S310 Data Sheet
10.5
Register Descriptions......................................................................................................................... 176
11.
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.4
11.5
Universal Asynchronous Receivers/Transmitters (UARTs).......................................... 197
Block Diagram ................................................................................................................................... 198
Functional Description ....................................................................................................................... 198
Transmit/Receive Logic ..................................................................................................................... 198
Baud-Rate Generation ....................................................................................................................... 199
Data Transmission ............................................................................................................................. 200
FIFO Operation .................................................................................................................................. 200
Interrupts............................................................................................................................................ 200
Loopback Operation .......................................................................................................................... 201
Initialization and Configuration........................................................................................................... 201
Register Map ..................................................................................................................................... 202
Register Descriptions......................................................................................................................... 203
12.
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.3
12.4
12.5
Synchronous Serial Interface (SSI) ................................................................................. 233
Block Diagram ................................................................................................................................... 233
Functional Description ....................................................................................................................... 234
Bit Rate Generation ........................................................................................................................... 234
FIFO Operation .................................................................................................................................. 234
Interrupts............................................................................................................................................ 234
Frame Formats .................................................................................................................................. 235
Initialization and Configuration........................................................................................................... 242
Register Map ..................................................................................................................................... 243
Register Descriptions......................................................................................................................... 244
13.
13.1
13.2
13.2.1
13.3
13.4
13.5
Analog Comparators......................................................................................................... 268
Block Diagram ................................................................................................................................... 268
Functional Description ....................................................................................................................... 269
Internal Reference Programming....................................................................................................... 270
Initialization and Configuration........................................................................................................... 271
Register Map ..................................................................................................................................... 272
Register Descriptions......................................................................................................................... 272
14.
14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
14.2.7
14.2.8
14.3
14.4
14.5
Pulse Width Modulator (PWM) ......................................................................................... 280
Block Diagram ................................................................................................................................... 280
Functional Description ....................................................................................................................... 280
PWM Timer ........................................................................................................................................ 280
PWM Comparators ............................................................................................................................ 281
PWM Signal Generator ...................................................................................................................... 282
Dead-Band Generator ....................................................................................................................... 283
Interrupt Selector ............................................................................................................................... 283
Synchronization Methods .................................................................................................................. 283
Fault Conditions ................................................................................................................................. 284
Output Control Block.......................................................................................................................... 284
Initialization and Configuration........................................................................................................... 284
Register Map ..................................................................................................................................... 285
Register Descriptions......................................................................................................................... 287
October 6, 2006
Preliminary
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