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PR E LI MIN ARY

LM3S2016 Microcontroller

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LM3S2016 Microcontroller

Table of Contents

About This Document .................................................................................................................... 18

Audience ..............................................................................................................................................

About This Manual ................................................................................................................................

Related Documents ...............................................................................................................................

Documentation Conventions ..................................................................................................................

1.1

1.2

1.3

1.4

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

Architectural Overview ...................................................................................................... 20

Product Features ......................................................................................................................

Target Applications ....................................................................................................................

High-Level Block Diagram .........................................................................................................

Functional Overview ..................................................................................................................

ARM Cortex™-M3 .....................................................................................................................

Motor Control Peripherals ..........................................................................................................

Analog Peripherals ....................................................................................................................

Serial Communications Peripherals ............................................................................................

System Peripherals ...................................................................................................................

Memory Peripherals ..................................................................................................................

Additional Features ...................................................................................................................

Hardware Details ......................................................................................................................

Block Diagram ..........................................................................................................................

Functional Description ...............................................................................................................

Serial Wire and JTAG Debug .....................................................................................................

Embedded Trace Macrocell (ETM) .............................................................................................

Trace Port Interface Unit (TPIU) .................................................................................................

ROM Table ...............................................................................................................................

Memory Protection Unit (MPU) ...................................................................................................

Nested Vectored Interrupt Controller (NVIC) ................................................................................

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

ARM Cortex-M3 Processor Core ...................................................................................... 33

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.3

5.4

5.4.1

5.4.2

Memory Map ....................................................................................................................... 39

Interrupts ............................................................................................................................ 41

JTAG Interface .................................................................................................................... 43

Block Diagram ..........................................................................................................................

Functional Description ...............................................................................................................

JTAG Interface Pins ..................................................................................................................

JTAG TAP Controller .................................................................................................................

Shift Registers ..........................................................................................................................

Operational Considerations ........................................................................................................

Initialization and Configuration ...................................................................................................

Register Descriptions ................................................................................................................

Instruction Register (IR) .............................................................................................................

Data Registers ..........................................................................................................................

6.1

6.1.1

6.1.2

System Control ................................................................................................................... 54

Functional Description ............................................................................................................... 54

Device Identification .................................................................................................................. 54

Reset Control ............................................................................................................................ 54

November 30, 2007

Preliminary

Table of Contents

6.1.3

6.1.4

6.1.5

6.2

6.3

6.4

Power Control ...........................................................................................................................

Clock Control ............................................................................................................................

System Control .........................................................................................................................

Initialization and Configuration ...................................................................................................

Register Map ............................................................................................................................

Register Descriptions ................................................................................................................

7.1

7.2

7.2.1

7.2.2

7.3

7.3.1

7.3.2

7.4

7.5

7.6

Internal Memory ............................................................................................................... 109

Block Diagram ........................................................................................................................ 109

Functional Description ............................................................................................................. 109

SRAM Memory ........................................................................................................................ 109

Flash Memory ......................................................................................................................... 110

Flash Memory Initialization and Configuration ........................................................................... 111

Flash Programming ................................................................................................................. 111

Nonvolatile Register Programming ........................................................................................... 112

Register Map .......................................................................................................................... 112

Flash Register Descriptions (Flash Control Offset) ..................................................................... 113

Flash Register Descriptions (System Control Offset) .................................................................. 120

8.1

8.1.1

8.1.2

8.1.3

8.1.4

8.1.5

8.1.6

8.2

8.3

8.4

General-Purpose Input/Outputs (GPIOs) ....................................................................... 133

Functional Description ............................................................................................................. 133

Data Control ........................................................................................................................... 134

Interrupt Control ...................................................................................................................... 135

Mode Control .......................................................................................................................... 136

Commit Control ....................................................................................................................... 136

Pad Control ............................................................................................................................. 136

Identification ........................................................................................................................... 136

Initialization and Configuration ................................................................................................. 136

Register Map .......................................................................................................................... 137

Register Descriptions .............................................................................................................. 139

9.1

9.2

9.2.1

9.2.2

9.2.3

9.3

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9.4

9.5

General-Purpose Timers ................................................................................................. 174

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

GPTM Reset Conditions ..........................................................................................................

32-Bit Timer Operating Modes ..................................................................................................

16-Bit Timer Operating Modes ..................................................................................................

Initialization and Configuration .................................................................................................

32-Bit One-Shot/Periodic Timer Mode .......................................................................................

32-Bit Real-Time Clock (RTC) Mode .........................................................................................

16-Bit One-Shot/Periodic Timer Mode .......................................................................................

16-Bit Input Edge Count Mode .................................................................................................

16-Bit Input Edge Timing Mode ................................................................................................

16-Bit PWM Mode ...................................................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

174

175

176

177

181

182

183

184

185

10.1

10.2

10.3

Watchdog Timer ............................................................................................................... 210

Block Diagram ........................................................................................................................ 210

Functional Description ............................................................................................................. 210

Initialization and Configuration ................................................................................................. 211

Preliminary

November 30, 2007

LM3S2016 Microcontroller

10.4

10.5

Register Map .......................................................................................................................... 211

Register Descriptions .............................................................................................................. 212

11.1

11.2

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.3

11.3.1

11.3.2

11.4

11.5

Analog-to-Digital Converter (ADC) ................................................................................. 233

Block Diagram ........................................................................................................................ 234

Functional Description ............................................................................................................. 234

Sample Sequencers ................................................................................................................ 234

Module Control ........................................................................................................................ 235

Hardware Sample Averaging Circuit ......................................................................................... 236

Analog-to-Digital Converter ...................................................................................................... 236

Test Modes ............................................................................................................................. 236

Initialization and Configuration ................................................................................................. 236

Module Initialization ................................................................................................................. 236

Sample Sequencer Configuration ............................................................................................. 236

Register Map .......................................................................................................................... 237

Register Descriptions .............................................................................................................. 238

12.1

12.2

12.2.1

12.2.2

12.2.3

12.2.4

12.2.5

12.2.6

12.2.7

12.2.8

12.3

12.4

12.5

Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 265

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Transmit/Receive Logic ...........................................................................................................

Baud-Rate Generation .............................................................................................................

Data Transmission ..................................................................................................................

Serial IR (SIR) .........................................................................................................................

FIFO Operation .......................................................................................................................

Interrupts ................................................................................................................................

Loopback Operation ................................................................................................................

IrDA SIR block ........................................................................................................................

Initialization and Configuration .................................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

Bit Rate Generation .................................................................................................................

FIFO Operation .......................................................................................................................

Interrupts ................................................................................................................................

Frame Formats .......................................................................................................................

Initialization and Configuration .................................................................................................

Register Map ..........................................................................................................................

Register Descriptions ..............................................................................................................

Block Diagram ........................................................................................................................

Functional Description .............................................................................................................

C Bus Functional Overview ....................................................................................................

Available Speed Modes ...........................................................................................................

Interrupts ................................................................................................................................

Loopback Operation ................................................................................................................

Command Sequence Flow Charts ............................................................................................

266

267

268

269

270

271

272

306

307

308

315

316

317

343

344

346

347

348

13.1

13.2

13.2.1

13.2.2

13.2.3

13.2.4

13.3

13.4

13.5

Synchronous Serial Interface (SSI) ................................................................................ 306

14.1

14.2

14.2.1

14.2.2

14.2.3

14.2.4

14.2.5

Inter-Integrated Circuit (I

C) Interface ............................................................................ 343

November 30, 2007

Preliminary

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器件捷径: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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