P RE L I M I NA R Y
LM3S101 Microcontroller
DATA SHEET
DS -LM3S 101- 00
C opyr ight © 2006 Lumi nary Micro , Inc.
LM3S101 Data Sheet
Legal Disclaimers and Trademark Information
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS,
LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO’S PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT
OR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO’S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL,
LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS.
Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro
sales office or your distributor to obtain the latest specifications before placing your product order.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to
them.
Copyright © 2006 Luminary Micro, Inc. All rights reserved. Stellaris and the Luminary Micro logo are trademarks of Luminary Micro, Inc. or its
subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited.
Other names and brands may be claimed as the property of others.
Luminary Micro, Inc.
2499 South Capital of Texas Hwy, Suite A-100
Austin, TX 78746
Main: +1-512-279-8800
Fax: +1-512-279-8879
http://www.luminarymicro.com
March 22, 2006
Preliminary
2
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revision History ............................................................................................................................. 12
About This Document..................................................................................................................... 13
Audience........................................................................................................................................................... 13
About This Manual............................................................................................................................................ 13
Related Documents .......................................................................................................................................... 13
Documentation Conventions............................................................................................................................. 13
1.
1.1
1.2
1.3
1.4
1.5
Architectural Overview............................................................................................................ 16
Product Features ...................................................................................................................................... 16
Target Applications ................................................................................................................................... 19
High-Level Block Diagram ........................................................................................................................ 20
Functional Overview ................................................................................................................................. 21
System Block Diagram.............................................................................................................................. 25
2.
ARM Cortex-M3 Processor Core ............................................................................................ 26
2.1 Block Diagram........................................................................................................................................... 27
2.2 Functional Description .............................................................................................................................. 27
3.
4.
5.
Memory Map ............................................................................................................................. 29
Interrupts .................................................................................................................................. 31
JTAG Interface ......................................................................................................................... 34
5.1 Block Diagram........................................................................................................................................... 35
5.2 Functional Description .............................................................................................................................. 35
5.3 Register Descriptions ................................................................................................................................ 39
6.
System Control ........................................................................................................................ 44
6.1 Functional Description .............................................................................................................................. 44
6.2 Register Map............................................................................................................................................. 49
6.3 Register Descriptions ................................................................................................................................ 51
7.
7.1
7.2
7.3
7.4
7.5
Internal Memory ....................................................................................................................... 80
Block Diagram........................................................................................................................................... 80
Functional Description .............................................................................................................................. 80
Initialization and Configuration .................................................................................................................. 82
Register Map............................................................................................................................................. 83
Register Descriptions ................................................................................................................................ 83
8.
8.1
8.2
8.3
8.4
8.5
General-Purpose Input/Outputs (GPIOs)............................................................................... 93
Block Diagram........................................................................................................................................... 94
Functional Description .............................................................................................................................. 94
Initialization and Configuration .................................................................................................................. 97
Register Map............................................................................................................................................. 98
Register Descriptions ................................................................................................................................ 99
9.
9.1
9.2
9.3
9.4
9.5
General-Purpose Timers ....................................................................................................... 130
Block Diagram......................................................................................................................................... 131
Functional Description
............................................................................................................................ 131
Initialization and Configuration ................................................................................................................ 137
Register Map........................................................................................................................................... 140
Register Descriptions .............................................................................................................................. 140
3
Preliminary
March 22, 2006
LM3S101 Data Sheet
10. Watchdog Timer..................................................................................................................... 160
10.1 Block Diagram......................................................................................................................................... 160
10.2 Functional Description ............................................................................................................................ 161
10.3 Initialization and Configuration ................................................................................................................ 161
10.4 Register Map........................................................................................................................................... 161
10.5 Register Descriptions .............................................................................................................................. 162
11. Universal Asynchronous Receiver/Transmitter (UART) .................................................... 182
11.1 Block Diagram......................................................................................................................................... 183
11.2 Functional Description ............................................................................................................................ 183
11.3 Initialization and Configuration ................................................................................................................ 186
11.4 Register Map........................................................................................................................................... 187
11.5 Register Descriptions .............................................................................................................................. 188
12. Synchronous Serial Interface (SSI)...................................................................................... 218
12.1 Block Diagram......................................................................................................................................... 218
12.2 Functional Description ............................................................................................................................ 219
12.3 Initialization and Configuration ................................................................................................................ 227
12.4 Register Map........................................................................................................................................... 228
12.5 Register Descriptions .............................................................................................................................. 228
13. Analog Comparators ............................................................................................................. 251
13.1 Block Diagram......................................................................................................................................... 251
13.2 Functional Description ............................................................................................................................ 251
13.3 Register Map........................................................................................................................................... 254
13.4 Register Descriptions .............................................................................................................................. 254
14. Pin Diagram............................................................................................................................ 262
15. Signal Tables.......................................................................................................................... 263
16. Operating Characteristics..................................................................................................... 270
17. Electrical Characteristics...................................................................................................... 271
17.1 DC Characteristics .................................................................................................................................. 271
17.2 AC Characteristics .................................................................................................................................. 273
18. Package Information ............................................................................................................. 282
Contact Information...................................................................................................................... 283
Ordering Information ....................................................................................................................................... 283
Development Kit ............................................................................................................................................. 283
March 22, 2006
Preliminary
4
List of Figures
Figure 1-1.
Figure 1-2.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 11-1.
Figure 11-2.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 12-6.
Figure 12-7.
Figure 12-8.
Figure 12-9.
Figure 12-10.
Figure 12-11.
Figure 12-12.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 14-1.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 17-4.
Figure 17-5.
Figure 17-6.
Stellaris High-Level Block Diagram ........................................................................................... 20
Stellaris System-Level Block Diagram....................................................................................... 25
CPU High-Level Block Diagram ............................................................................................... 27
TPIU Block Diagram .................................................................................................................. 28
JTAG Module Block Diagram .................................................................................................... 35
Test Access Port State Machine ............................................................................................... 38
IDCODE Register Format.......................................................................................................... 42
BYPASS Register Format ......................................................................................................... 42
Boundary Scan Register Format ............................................................................................... 43
External Circuitry to Extend Reset............................................................................................. 45
Main Clock Tree ........................................................................................................................ 48
Flash Block Diagram ................................................................................................................. 80
GPIO Module Block Diagram .................................................................................................... 94
GPIO Port Block Diagram.......................................................................................................... 95
GPIODATA Write Example........................................................................................................ 95
GPIODATA Read Example ....................................................................................................... 96
GPTM Block Diagram.............................................................................................................. 131
16-Bit Input Edge Count Mode Example ................................................................................. 135
16-Bit Input Edge Time Mode Example................................................................................... 136
16-Bit PWM Mode Example .................................................................................................... 137
Watchdog Timer Block Diagram.............................................................................................. 160
UART Block Diagram .............................................................................................................. 183
UART Character Frame........................................................................................................... 184
SSI Block Diagram .................................................................................................................. 218
TI Synchronous Serial Frame Format (Single Transfer).......................................................... 220
TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 221
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 222
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 222
Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 223
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 223
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 224
Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 224
National Semiconductor MICROWIRE Frame Format (Single Frame) ................................... 225
National Semiconductor MICROWIRE Frame Format (Continuous Transfers) ...................... 226
National Semiconductor MICROWIRE Frame Format, SSIFss Input Setup
and Hold Requirements........................................................................................................... 227
Analog Comparator Block Diagram ......................................................................................... 251
Structure of Comparator Unit................................................................................................... 252
Comparator Internal Reference Structure ............................................................................... 253
Pin Connection Diagram.......................................................................................................... 262
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 275
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer................................. 276
SSI Timing for SPI Frame Format (FRF=00), with SPH=1...................................................... 276
JTAG Test Clock Input Timing................................................................................................. 277
JTAG Boundary Scan Timing .................................................................................................. 278
JTAG Test Access Port (TAP) Timing ..................................................................................... 278
5
Preliminary
March 22, 2006
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