MX25L2005
2M-BIT [x 1] CMOS SERIAL FLASH
FEATURES
GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0
and Mode 3
• 2,097,152 x 1 bit structure
• 64 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 4 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 85MHz serial clock (15pF + 1TTL
Load) and 66MHz serial clock (30pF + 1TTL Load)
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page
(256-byte per page)
- Fast erase time: 60ms(typ.) and 120ms(max.)/sector
(4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-
byte per block)
• Low Power Consumption
- Low active read current: 12mA(max.) at 85MHz,
8mA(max.) at 66MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (max.)
- Low active erase current: 15mA (max.)
- Low standby current: 10uA (max.)
- Deep power-down mode 1uA (typical)
• Minimum 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP1 status bit defines the size of the area
to be software protected against Program and Erase
instructions
• Auto Erase and Auto Program Algorithm
-
Automatically erases and verifies data at selected
sector
-
Automatically programs and verifies data at selected
page by an internal algorithm that automatically times
the program pulse widths (Any page to be programed
should have page in the erased state first)
•
Status Register Feature
•
Electronic Identification
-
JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
HARDWARE FEATURES
•
SCLK Input
-
Serial clock input
• SI Input
-
Serial Data Input
• SO Output
-
Serial Data Output
• WP# pin
-
Hardware write protection
• HOLD# pin
-
pause the chip without diselecting the chip
• PACKAGE
-
8-pin SOP (150mil)
- 8-land SON (6x5mm)
-
All Pb-free devices are RoHS Compliant
P/N: PM1239
REV. 1.3, NOV. 06, 2006
1
MX25L2005
GENERAL DESCRIPTION
The MX25L2005 is a CMOS 2,097,152 bit serial Flash
memory, which is configured as 262,144 x 8 internally. The
MX25L2005 feature a serial peripheral interface and soft-
ware protocol allowing operation on a simple 3-wire bus.
The three bus signals are a clock input (SCLK), a serial
data input (SI), and a serial data output (SO). SPI access
to the device is enabled by CS# input.
The MX25L2005 provide sequential read operation on
whole chip.
After program/erase command is issued, auto program/
erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed.
Program command is executed on page (256 bytes) basis,
and erase command is executes on chip or sector(4K-
bytes) or block(64K-bytes).
To provide user with ease of interface, a status register is
included to indicate the status of the chip. The status read
command can be issued to detect completion status of a
program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is
put in standby mode and draws less than 10uA DC current.
The MX25L2005 utilize MXIC's proprietary memory cell,
which reliably stores memory contents even after 100,000
program and erase cycles.
PIN CONFIGURATIONS
8-PIN SOP (150mil)
VCC
HOLD#
SCLK
SI
PIN DESCRIPTION
SYMBOL
CS#
SI
SO
SCLK
HOLD#
VCC
GND
DESCRIPTION
Chip Select
Serial Data Input
Serial Data Output
Clock Input
Hold, to pause the device without
deselecting the device
+ 3.3V Power Supply
Ground
8-LAND SON (6x5mm)
CS#
SO
WP#
GND
CS#
SO
WP#
GND
1
2
3
4
8
7
6
5
VCC
HOLD#
SCLK
SI
P/N: PM1239
1
2
3
4
8
7
6
5
2
REV. 1.3, NOV. 06, 2006
MX25L2005
BLOCK DIAGRAM
Address
Generator
X-Decoder
Memory Array
Page Buffer
Data
Register
Y-Decoder
SRAM
Buffer
Sense
Amplifier
HV
Generator
SI
CS#
Mode
Logic
State
Machine
Output
Buffer
SO
SCLK
Clock Generator
P/N: PM1239
3
REV. 1.3, NOV. 06, 2006
MX25L2005
DATA PROTECTION
The MX25L2005 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transition. During power up the device automatically resets
the state machine in the Read mode. In addition, with its
control register architecture, alteration of the memory
contents only occurs after successful completion of
specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting from VCC power-up and power-down
transition or system noise.
•
Power-on reset and tPUW: to avoid sudden power
switch by system power supply transition, the power-
on reset and tPUW (internal timer) may protect the
Flash.
other command to change data. The WEL bit will return
to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
•
Software Protection Mode (SPM): by using BP0-BP2
bits to set the part of Flash protected from data change.
Hardware Protection Mode (HPM): by using WP# going
low to protect the BP0-BP2 bits and SRWD bit from data
change.
Deep Power Down Mode: By entering deep power down
mode, the flash device also is under protected from
writing all commands except Release from deep power
down mode command (RDP) and Read Electronic
Signature command (RES).
•
• Valid command length checking: The command length
will be checked whether it is at byte base and com-
pleted on byte boundary.
• Write Enable (WREN) command: WREN command is
required to set the Write Enable Latch bit (WEL) before
•
P/N: PM1239
4
REV. 1.3, NOV. 06, 2006
MX25L2005
Table 1. Protected Area Sizes
Status bit
BP1
BP0
0
0
0
1
1
0
1
1
Protect level
0 (none)
1 (1 block)
2 (2 blocks)
3 (All)
2Mb
None
Block 3
Block 2-3
All
HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation
of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial
Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock
signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is
being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.
Figure 1. Hold Condition Operation
CS#
SCLK
HOLD#
Hold
Condition
(standard)
Hold
Condition
(non-standard)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during
the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device.
To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
P/N: PM1239
5
REV. 1.3, NOV. 06, 2006
FPGA/CPLD
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