ST7554
V.90 USB WORLD MODEM CONTROLLER
SUMMARY DATA
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GENERAL
USB HOT PLUG & PLAY INTERFACE
DIRECT INTERFACE TO ST MAFE+DAA
CHIP-SET ST75951/ST952 FOR WORLD-
WIDE DAA DESIGN OR TO STLC7550 FOR
TRADITIONAL DAA DESIGN
WINDOWS® 98 AND NT 5.0 SUPPORT
TAPI 2.0 COMPLIANT
SOFTWARE UPGRADABLE
MINIMUM SYSTEM REQUIREMENTS:
USB MOTHERBOARD, 166MHz PENTIUM®
PROCESSOR WITH MMX™ TECHNOLOGY,
WINDOWS® 98 AND 16MBYTES RAM OR
WINDOWS® NT 5.0 AND 32MBYTES RAM
DEVICE FEATURES
SINGLE 9.216MHz CRYSTAL OSCILLATOR
INTEGRATED ANALOG AND DIGITAL 3.3V
REGULATORS
DEDICATED PINS FOR RING, OFF-HOOK,
CLID, LOOP CURRENT SENSE
0.5µm CMOS PROCESS
TQFP48 (7 x 7 mm) PACKAGE
DATA MODEM / FAX / VOICE
V.90
V.34BIS, V.34, V.32BIS, V.32, V.22BIS, V.22,
V.23, V.21
BELL 103 AND BELL 212A
V.17, V.27TER, V.29, FAX CLASS 1 SUPPORT
V.42, V.42BIS, MNP 2, 3, 4, 5
V.80
V.8 AND AUTO MODE
VOICE / FAX / MODEM DISTINCTION
ADPCM VOICE COMPRESSION/DECOM-
PRESSION
VOICE DETECTION (SILENCE DETECTION)
OTHER FEATURES
VIRTUAL UART (460.8Kbps)
AT HAYES COMMAND COMPATIBLE
TIME INDEPENDENT ESCAPE SEQUENCE
(TIES) COMMAND
CALLER ID
TQFP48
(7 x 7 x 1.40mm)
(Full Plastic Quad Flat Pack)
ORDER CODE :
ST7554TQF7
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DTMF DETECTION AND GENERATION
WAKE UP ON RING
WORLD-WIDE PROGRAMMABLE SILICON
DAA SUPPORT FOR ST75951/ST952
MAFE+DAA CHIP-SET
UNIVERSAL SERIAL BUS
SPECIFICATION 1.0, 12MBps FULL SPEED
ON-CHIP USB TRANSCEIVER WITH DIGITAL PLL
COMMUNICATION DEVICE CLASS AND
VENDOR REQUESTS
BUS OR SELF POWERED APPLICATION
(PIN-PROGRAMMABLE)
ONNOW POWER MANAGEMENT (D0, D2, D3)
LOW POWER CONSUMPTION (SUSPEND
MODE D2), WHOLE APPLICATION BELOW
500µA
DESCRIPTION
The ST7554 is a single chip host signal processing
Modem/fax/voice controller that supports data rates
up to 56Kbps. All data pump and protocol functions
are executed on the host PC’s processor. This
product has been developed in cooperation with
Smart Link Ltd, who ported "USB-Modio", its host
based Modem and system software into ST system
and hardware platform. The ST7554 directly con-
nects to ST high performance Modem analog front-
end (MAFE) STLC7550 or to the highly integrated
MAFE+DAA chip-set ST75951/ST952. The ST7554
also features an Universal Serial Bus (USB) inter-
face for direct connection to the host PC for maxi-
mum flexibility and real plug & play operation.
1/11
January 1999
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
RESERVED
36
35
34
33
32
31
30
29
28
27
26
25
RESERVED
DAASEL
PDOWN
DGND
DOUT
MCLK
TRxD
HC1
DIN
DC
FS
BUZEN
PULSE
DISHS
RFC
LED
CD
CLID
RESERVED
HO
45
46
47
48
HSDT
RESERVED
RI
44
43
42
41
40
39
38
37
24
23
22
21
20
19
18
17
16
15
14
13
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
10
11
GNDBUS
PSM
PIN CONNECTIONS
ST7554
XTALOUT
FLTPLL
VREGD
XTALIN
VREGA
RESET
D+
D-
AGND
VBUS
12
1
2
3
4
5
6
7
8
9
2/11
7554S-01.EPS
ST7554
PIN LIST
Name
XTALIN
XTALOUT
RESET
VBUS
GNDBUS
VREGA
VREGD
PSM
D+
D-
TRxD
DC
BUZEN
PULSE
DISHS
RFC
LED
CD
CLID
HO
HSDT
RI
HC1
PDOWN
MCLK
DAASEL
FS
DOUT
DIN
FLTPLL
DGND
AGND
RESERVED
RESERVED
Pin
9
10
12
5
3
6
4
8
2
1
35
36
37
38
39
40
41
42
43
45
46
48
27
26
29
34
28
31
30
11
32
7
13 to 25-33-44
47
Type
I
O
I
I
I
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
O
I
OA
I
I
-
-
Crystal Input
Crystal Output
Reset Function to initialise the device (active low)
Positive Voltage Regulator Input, connected to USB VBUS
Regulator Ground, connected to USB Ground (0V) (see Note 1)
Positive Regulated Analog Input/Output Power Supply
Positive Regulated Digital Input/Output Power Supply
Power Supply Mode (Bus-powered or Self-powered)
Positive Data Signal of Differential Data Bus conforming to USB Standard
Specification 1.0
Negative Data Signal of Differential Data Bus conforming to USB Standard
Specification 1.0
Transmit/Receive Data Led
DC mask
Buzzer Amplifier Enable/Mute
Pulse dialing
Disconnect external phone
Refresh
LED control
Carrier Detect Led
Caller ID
Hook Control
Current sense
Ring Indicator
Modem Codec Hardware Control mode selection
SSI Powerdown bit output (active low)
SSI Master Clock Output
Select Silicon or Discrete DAA Configuration Mode
SSI Frame Synchronisation Input
SSI Serial Data Output
SSI Serial Data Input
PLL filter analog output. Must be connected to analog ground AGND with
33pF capacitor
Digital Ground (0V) (see Note 1)
Analog Ground (0V) (see Note 1)
Not connected
Connect to digital ground DGND
7554S-01.TBL
Description
Note 1 :
Analog and digital ground pins must be tied together to USB ground GNDBUS.
3/11
ST7554
PIN DESCRIPTION
1 - Power Supply
(7 pins)
1.1 - Regulator Input Power Supply
(VBUS)
This pin must be connected to USB VBUS (+5V).
It supplies the integrated analog USB transceiver.
It is also the positive regulator power supply input
(5V) when ST7554 is in bus-powered mode
(PSM = 1) and it is used to internally generate the
3.3V supply for the digital and analog circuitry.
1.2 - Regulated Analog V
DD
Supply
(VREGA)
This pin is the analog power supply input (PSM = 0)
or analog 3.3V power supply output (PSM = 1).
This pin is the positive analog power supply for the
external Codec and DAA.
It is recommended to add a 1µF capacitor between
VREGA and GNDA as close as possible to the
IC pins.
1.3 - Regulated V
DD
Supply
(VREGD)
This pin is the digital power supply input (PSM = 0)
or digital 3.3V power supply output (PSM = 1).
This pin is the positive digital power supply for the
external Codec and DAA.
It is recommended to add a 1µF capacitor between
VREGA and GNDA as close as possible to the
IC pins.
1.4 - Power Supply Mode
(PSM)
This pin controls the VREGD and VREGA power
supply mode.
When PSM = 1, the application is bus-powered.
The 3.3V power supply is generated internally from
VBUS. In this case VREGD and VREGA are out-
puts which can be used to supply 3.3V to external
devices (see Figure 1).
When PSM = 0, the application is self-powered.
VBUS must be still connected to the VBUS Pin of
the USB connector in order to supply the integrated
USB transceiver. Anyway in this case VREGD and
VREGA must be fed by a 3.3V externally regulated
digital and analog power supplies (see Figure 2).
1.5 - Ground
(DGND, AGND and GNDBUS)
DGND, AGND and GNDBUS are the digital, analog
and USB ground return pins respectively.
They should be connected together outside the
chip to the GND pin of the USB plug.
Figure 1 :
ST7554 in Bus-Powered mode
(PSM = 1)
ST7554
8 PSM
5 VBUS
from USB
3 GNDBUS
4 VREGD
to other
digital ICs
32 DGND
6 VREGA
7554S-02.EPS
7554S-03.EPS
to other
analog ICs
7 AGND
Figure 2 :
ST7554 in Self Powered mode
(PSM = 0)
ST7554
8 PSM
5 VBUS
from USB
3 GNDBUS
4 VREGD
from 3.3V
externally
regulated
supplies
32 DGND
6 VREGA
7 AGND
2 - USB Interface
(D+ , D-)
These pins are the positive and negative USB
differential data lines. They shall be both connected
to the USB plug or USB protection circuit via 27Ω
series resistors for line impedance matching.
4/11
ST7554
PIN DESCRIPTION
(continued)
3 - Reset, Powerdown
(RESET, PDOWN)
RESET Pin initialises the internal counters and
control registers to their default value. A minimum
low pulse of 1ms is required to reset the chip.
In a typical application RESET is connected to
VBUS through a R, C network. This ensures that
the chip is reset at each connection / disconnection
to the USB bus (see Figure 3).
PDOWN Pin shall be connected to the powerdown
inputs of the external codec used on the SSI.
When ST7554 is in Suspend mode, PDOWN is
forced low so that the external codec is in
powerdown.
Figure 3 :
RC network for RESET
VBUS
based on ST75951 + ST952. Connect to DGND
when using STLC7550 with discrete interface.
5 - DAA Control Pins
(IMP, DC, BUZEN,
PULSE, DISHS, RFC, LED, CLID, HO, HSDT, RI)
These pins control the World Wide software
programmable DAA through ST75951/ST952.
6 - Crystal
(XTALIN, XTALOUT)
These pins must be tied to the 9.216MHz external
crystal.
It is recommended to use a
±50ppm
fundamental
parallel resonator crystal. It is recommended to
insert a 1.8kΩ resistor between XTALOUT and the
crystal to limit its energy to 100µW for a 20Ω
resonator (see Figure 4).
For a SMD crystal the load capacitor is typically
C
LOAD
= 12pF and this leads to an ideal value of
C = 24pF for the capacitors between the crystal
and analog ground (AGND). Anyway, in practice
these capacitors shall be reduced down to
C = 18pF each by considering parasitic capacitors
on PCB and package (see Figure 4).
After a reset or when leaving the suspend state,
the 9.216MHz is asserted inside ST7554 only
3.5ms later in order to wait for it to be stable.
Figure 4 :
Application schematic for the
9.216MHz external crystal
XTAL
IN
9
XTAL
OUT
10
R
1.8k
W
R
220k
W
12 RESET
C
10nF
7554S-04.EPS
4 - Serial Synchronous Interface
ST7554 has a Serial Syncronous Interface (SSI)
dedicated to the connection of the STLC7550 or
ST75951, ST high performance Modem Analog
Front-End (MAFE).
4.1 - Data
(DIN, DOUT)
Digital data word input/output of SSI, to be con-
nected to the data word pins of STLC7550 or
ST75951.
4.2 - Master Clock
(MCLK)
This pin is the master clock output.
4.3 - Frame Synchronization
(FS)
The frame synchronization is used to synchronize data
transfer between ST7554 and the external Codec.
4.4 - Hardware Control
(HC1)
HC1 must be connected to the corresponding pin of
STLC7550 or ST75951, while their HC0 Pin shall be
tied to the 3.3V VREGD digital supply. This pin
selects data or control modes for the Modem Codec.
4.5 - DAA Selection
(DAASEL)
Connect to VREGD when using silicon DAA chipset
AGND
AGND
7 - PLL Output Filter
(FLTPLL)
This pin must be connected to the analog ground
(AGND) through a 33pF capacitor.
8 - Reserved Pins
(18 pins)
These pins must be left not connected except
Pin 47 which should be connected to the digital
ground DGND.
5/11
7554S-05.EPS
C
18pF
C
18pF
嵌入式系统
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