ST75C520
HIGH SPEED FAX MODEM DATA PUMP
.
.
.
.
.
.
.
.
PRELIMINARY DATA
ITU-T V.17, V.29, V.27ter, V.21 WITH FAX
SUPPORT
ITU-T V.23, V.21, BELL 103
V.17, V.29 (T104), V.27ter SHORT TRAINS
V.33 HALF-DUPLEX
1800Hz OR 1700Hz CARRIER
SINGLE CHIP COMPLETE DATA PUMP
SINGLE 5V POWER SUPPLY :
- TYPICAL ACTIVE POWER CONSUMPTION :
375mW
- LOW POWER MODE (typ. 5mW)
EXTENDED MODES OF OPERATIONS :
- FULL IMPLEMENTATION OF THE V.17,
V.33, V.29 AND V.27ter HANDSHAKES
- AUTODIAL AND AUTOANSWER CAPABIL-
ITY
- PROGRAMMABLE TONE DETECTION AND
FSK V.21 FLAG PATTERN DETECTION
DURING HIGH SPEED RECEPTION
- PROGRAMMABLE CALL PROGRESS AND
CALL WAITING TONE DETECTORS IN-
CLUDING DTMF
- PROGRAMMABLE CLASS™ DETECTION
CAPABILITY
- WIDE DYNAMIC RANGE (>48dB)
- A-LAW VOICE PCM MODE
VERSATILE INTERFACES :
- PARALLEL 64 x 8-BIT DUAL PORT RAM
- SYNCHRONOUS/HDLC PARALLEL DATA
HANDLING
- HDLC FRAMING SUPPORT
- V.24 INTERFACE
- FULL OPERATING STATUS REAL TIME
MONITORING
- FULL DIAGNOSTIC CAPABILITY
- DUAL 8-BIT DAC FOR CONSTELLATION
DISPLAY
DESCRIPTION
The SGS-THOMSON Microelectronics ST75C520
chip is a highly integrated modem engine, which
can operate with all currently used FAX group III
standards up to 14400bps. Full V.21, V.23 and Bell
103 full duplex modem standards are imple-
mented.
PQFP64
(Plastic Quad Flat Pack)
ORDER CODE :
ST75C520 PQFP
.
June 1995
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice.
1/45
ST75C520
CONTENTS
I
I.1
I.2
I.3
I.4
I.5
I.6
I.7
II
III
III.1
III.2
III.3
IV
IV.1
IV.2
IV.3
V.
V.1
V.2
V.3
V.4
V.5
VI
VII
VII.1
VII.2
VIII
VIII.1
VIII.2
VIII.3
IX
IX.1
IX.2
IX.3
IX.4
IX.5
IX.6
X
XI
XII
XIII
PIN DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN CONNECTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOST INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ANALOG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V.24 INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MISCELLANOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOUNDARY SCAN INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BLOCK DIAGRAMS.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ELECTRICAL SPECIFICATIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FUNCTIONAL DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USER INTERFACE.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DUAL PORT RAM DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMMAND SET SHORT FORM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STATUS - REPORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATA EXCHANGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMMAND SET DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STATUS DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMMAND ACKNOWLEDGE AND REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODEM STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TONE DETECTORS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFFER OPERATIONS.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RECEIVE OPERATIONS OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRANSMIT OPERATIONS OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BUFFER STATUS AND FORMAT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RECEIVE BUFFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATA BUFFER MANAGEMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEFAULT CALL PROGRESS TONE DETECTORS
. . . . . . . . . . . . . . . . . . . . . . . . . . .
DEFAULT ANSWER TONE DETECTORS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ELECTRICAL SCHEMATICS.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCB DESIGN GUIDELINES.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
3
3
3
4
4
4
4
5
5
6
6
6
8
10
10
10
11
11
11
14
16
17
17
18
27
27
28
34
34
34
38
38
38
39
39
40
40
40
42
42
42
43
2/45
ST75C520
I - PIN DESCRIPTION
I.1 - Pin Connections
EYEY
TEST1
TEST2
EYEX
TXA1
2
TXA2
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
AGNDT
V
CM
AV
DD
RXA2
RXA1
AGNDR
V
REFP
V
REFN
EXTAL
XTAL
CLKOUT
HALT
RESET
SCOUT
BOS
EOS
MC0
RING
GND
RXD
EBS
3
MC2
TXD
CTS
RTS
V
DD
CLK
CD
16 15 14 13 12 11 10 9
SA0
SA1
SA2
SA3
SA4
SA5
SA6
GND
V
DD
SD0
SD1
SD2
SD3
SD4
SD5
SD6
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
8
7
6
5
4
SR/W (SWR)
SDTACK
SCCLK
SDS (SRD)
INT/MOT
RDYS
SINTR
SCIN
GND
MC1
SD7
SCS
V
DD
MCI
I.2 - Host Interface
The exchanges with the control processor proceed through a 64 Bytes DUAL port RAM shared between
the ST75C520 and the Host. The signals associated with this interface are :
Pin Name
SD0..SD7
SA0..SA6
SDS (SRD)
SR/W (SWR)
SCS
SDTACK
SINTR
RESET
RING
INT/MOT
Type
I/O
I
I
I
I
OD
OD
I
I
I
Description
System Data Bus. 8-bit data bus used for asynchronous exchanges between the ST75C520
and the Host through the dual port RAM. High impedance when exchanges are not active.
System Address Bus. 7-bit address bus for dual port RAM.
System Data Strobe. Active low. Synchronizes all the exchanges. In Motorola mode initiates
the exchange, active low. In Intel mode initiates a read exchange, active low.
System Read/Write. In Motorola mode defines the type of exchange read/write. In Intel
mode initiates a write exchange, active low.
System Chip Select. Active low.
System Bus Data Acknowledge. Active low. Open drain.
System Interrupt Request. Active low. This signal is asserted by the ST75C520 and
negated by the host. Open drain.
Reset. Active low.
Ring Detect Signal. Active low.
Select Intel/Motorola Interface.
3/45
75C52001.EPS
ST75C520
I.3 - Analog Interface
Pin
Name
TXA1
TXA2
Type
O
O
Description
Transmit Analog Output 1
Transmit Analog Output 2. Outputs TXA1 and TXA2 provide analog signals with maximum peak to peak
amplitude 2 x V
REF
, and must be followed by an external continous-time two pole smoothing filter (where
V
REF
= V
REFP
- V
REFN
).
Receive Analog Input 1
Receive Analog Input 2. The analog differential input peak to peak signal must be less than 2 x V
REF
. It
must be preceded by an external continous-time single pole anti-aliasing filter. This filter must be as
close as possible to the RXA1 and RXA2 Pins (where V
REF
= V
REFP
- V
REFN
).
Analog Common Voltage (nominal +2.5V). This input must be decoupled with respect to AGND.
Analog Negative Reference (nominal V
CM
- 1.25V). This input must be decoupled with respect to V
CM
.
Analog Positive Reference (nominal V
CM
+1.25V). This input must be decoupled with respect to V
CM
.
RXA1
RXA2
I
I
V
CM
V
REFN
V
REFP
I/O
I
I
I.4 - V.24 Interface
Pin Name
RTS
CLK
CTS
RxD
TxD
CD
Type
I
O
O
O
I
O
Description
Request to Send. Active low.
Data Bit Clock. Falling edge coïncides with DATA change.
Clear to Send. Active low.
Receive Data
Transmit Data sampled with rising edge of CLK
Carrier Detect. Active low.
I.5 - Miscellaneous
Pin Name
XTAL
EXTAL
EYEX
EYEY
TEST1
TEST2
Type
O
I
O
O
Description
Internal Oscillator Output. Left open if not used.
Internal Oscillator Input, or External Clock
Constellation X analog coordinate
Constellation Y analog coordinate
To be left open
To be left open
Note :
The nominal external clock frequency of the ST75C520 is 29.4912MHz with a precision better than
±
5.10
-5
I.6 - Boundary Scan Interface
A set of 13 signals are dedicated for Testing the ST75C520 Component. These signals can be used in a
development phase, associated with the SGS-THOMSON ST18932 Boundary Scan Development Tools,
to Debug the application Hardware and Software. If not used all input signals must be grounded and all
output signals left open.
Pin Name
SCIN
SCCLK
SCOUT
BOS
EOS
MC0..MC2
HALT
MCI
RDYS
EBS
CLKOUT
Type
I
I
O
I
I
I
I
O
O
I
O
Description
Scan Data Input
Scan Clock
Scan Data Output
Begin of Scan Control
End of Scan
Mode Control
Stop ST75C520 Execution
Multicycle Instruction
Ready to Scan Flag
Enable Boundary Scan. Active low (must be set low in normal mode).
Internal ST75C520 Clock (XTAL frequency divided by 2)
4/45
ST75C520
I.7 - Power Supply
Symbol
V
DD
GND
AV
DD
AGNDT
AGNDR
Parameter
Digital +5V (Pin 9, 25, 41). To be connected to AV
DD
(see below).
Digital Ground (Pin 8, 24, 40). To be connected to AGNDT and AGNDR (see below).
Analog +5V (Pin 62). To be connected to V
DD
(see below).
Analog Transmit Ground (Pin 64). To be connected to GND (see below).
Analog Receive Ground (Pin 59). To be connected to GND (see below).
AGNDT and AGNDR must be connected together as close as possible to the chip.
GND and AGNDR board plans should be separated, then connected together as close as possible to the
chip, at a single point. Similarly V
DD
and AV
DD
must ne connected as close as possible to the chip, at a
single point.
II - BLOCK DIAGRAMS
II.1 - Functional Block Diagram
RXD
TXD
16
CLK
14
1
2
TXA2
TXA1
V.17, V.29, V.27
FAX TRANSMITTER
15
ST75C520
HDLC
TX
MUX
TX
ANALOG
SD [0..7]
(26 to 33)
DUAL RAM
INTERFACE
DPLL
HDLC
RX
V.17, V.29, V.27
FAX RECEIVER
RX
ANALOG
60 RXA1
61 RXA2
SINTR 38
HANDSHAKE AND
STATUS REPORT
TONE
DETECTOR
V.24
INTERFACE
RING
DETECTOR
V.21 FLAG
DETECTOR
13
CD
12
CTS
11
RTS
10
RING
5/45
75C52002.EPS
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
