®
ST9291
16-48K ROM HCMOS MCU WITH
ON SCREEN DISPLAY AND VOLTAGE TUNING OUTPUT
FUNCTIONAL DESCRIPTION
Register oriented 8/16 bit CORE with
RUN, WFI and HALT modes
Minimum instruction cycle time: 500ns
(12MHz internal)
16 to 48K bytes of ROM,
384/640 bytes of RAM,
224 general purpose registers available as RAM,
accumulators or index registers (Register File)
42-lead Shrink DIP package or
56-lead Shrink DIP package
Interrupt handler and Serial Peripheral Interface
as standard features
31 (42 pin package) / 42 (56 pin package) fully
programmable I/O pins
34 character x15 rows software programmable
On Screen Display module with colour, italic, un-
derline, flash, transparent and fringe attribute
options
14-bit Voltage Synthesis for tuning reference
voltage.
8 8-bit PWM D/A outputs with repetition frequency
2 to 32kHz and 12V Open Drain Capability
16 bit Timer with 8 bit Prescaler, able to be used
as a Watchdog Timer
16-bit programmable Slice Timer with 8-bit pres-
caler
3 channel Analog to Digital Converter, with inte-
gral sample and hold, fast 5.75µs conversion
time, 6-bit guaranteed resolution
Rich Instruction Set and 14 Addressing modes
Division-by-Zero trap generation
Versatile Development tools, including assembler,
linker, C-compiler, archiver, graphic oriented de-
bugger and hardware emulators
Real Time Operating System
Windowed EPROM parts available for prototyp-
ing and pre-production development phases
PSDIP42
PSDIP56
(Ordering Information at the end of the Datasheet)
DEVICE SUMMARY
Device
ST9291J2/N2
ST9291J3/N3
ST9291J4/N4
ST9291J5/N5
ST9291J6/N6
ST9291J7/N7
ROM
16K
16K
24K
24K
32K
48K
RAM
384
640
384
640
640
640
PACKAGE
PSDIP42/56
PSDIP42/56
PSDIP42/56
PSDIP42/56
PSDIP42/56
PSDIP42/56
July 1995
1/20
ST9291
Figure 1. 42 Pin Shrink DIP Pinout
42
41
40
Figure 2. 56 Pin Shrink DIP Pinout
1
2
3
56
55
54
1
2
3
19
20
21
24
23
22
VR01740B
26
27
28
31
30
29
VR01740A
ST9291J Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Pin
name
P2.0/INT7
RESET
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
P3.7
P3.6
P3.5
P3.4
P3.3/B
P3.2/G
P3.1/R
P3.0/FB
P5.1/SDIO
P5.0/SCK/INT2
V
DD
Pin
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Pin
name
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VSO1
P2.4/NMI
P2.5/AIN3/VSO2
OSCIN
OSCOUT
P4.7/PWM7/
EXTRG (AD)
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC
AV
DD
PLLR
PLLF
V
SS
ST9291N Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin
name
P2.1/INT5/AIN1
P2.0/INT7
RESET
P0.7
P0.6
P0.5
N.C
.(1)
Pin
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Pin
name
P2.2/INT0/AIN2
P2.3/INT6/VSO1
P2.4/NMI
P2.5/AIN3/VSO2
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
OSCIN
OSCOUT
P4.7/PWM7/
EXTRG (AD)
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC
AV
DD
PLLR
PLLF
V
SS
P0.4
P0.3
P0.2
P0.1
P0.0
N.C.
(1)
V
DD
(2)
(1)
N.C.
P3.7
P3.6
P3.5
P3.4
P3.3/B
P3.2/G
P3.1/R
P3.0/FB
P5.3
P5.2
P5.1/SDIO
P5.0/SCK/INT2
V
DD
(2)
Notes (N Package only) :
1. N.C. means “not connected”
2. Pins 14 and 28 (VDD) are internally connected
2/20
®
ST9291
GENERAL DESCRIPTION
The ST9291 is a ROM member of the ST9 family of
microcontrollers, completely developed and pro-
duced by SGS-THOMSON Microelectronics using
a proprietary n-well HCMOS process.
The ROM parts are fully compatible with their
EPROM and OTP (One-Time Programmable) ver-
sions, which may be used for the prototyping and
pre-production phases of development.
The nucleus of the ST9291 is the advanced ST9
Core which includes the Central Processing Unit
(CPU), the Register File, a 16-bit Timer/Watchdog
with 8-bit Prescaler, a Serial Peripheral Interface
supporting S-bus, I
2
C-bus and IM-bus Interface,
plus two 8-bit I/O ports. The Core has independent
memory and register buses allowing a high degree
of pipelining to add to the efficiency of the code
execution speed of the extensive instruction set.
The powerful I/O capabilities demanded by micro-
controller applications are fulfilled by the ST9291
with up to 32/42 I/O lines dedicated to digital In-
put/Output. These lines are grouped into up to six
I/O Ports and can be configured on a bit basis un-
der software control to provide timing, status sig-
nals, timer inputs and outputs, analog inputs, ex-
ternal interrupts, OSD (On Screen Display) output
and serial or parallel I/O.
Three basic memory spaces are available to sup-
port this wide range of configurations: Program
Memory, Data Memory and the Register File,
which includes the control and status registers of
the on-chip peripherals.
The human interface is provided by the On Screen
Display module, this can produce up to 15 lines of
up to 34 characters from a ROM defined 128 char-
acter set. The 9x13 character can be modified by 4
different pixel sizes, with character rounding, and
formed into words with colour and format attrib-
utes.
A 14-bit VS (Voltage Synthesis) output using the
PWM (Pulse Width Modulation)/BRM (Bit Rate
Modulation) is present to generate tuning voltages
for low-mid range TV set applications. The tuning
voltage is output on one of two separate output
pins.
A 16-bit Slice Timer with an 8-bit Prescaler is also
present.
Figure 3. ST9291 Block Diagram
16-Bit TIMER/WATCHDOG+SPI
16 k / 48 k Bytes
ROM or EPROM
(1)
384 / 640 Bytes
RAM
256 Bytes
REGISTER FILE
CPU
SLICE
TIMER
VOLTAGE
SYNTHESIS
MEMORY BUS ( Address & Data )
REGISTER BUS ( Address & Data )
I/O PORT 0
I/O PORT 2
( Analog Inputs )
A/D
Converter
I/O PORT
3
7
On Screen
Display
PLL
I/O PORT 4
P.W.M.
Outputs
8
AV
DD
P.W.M.
D/A
Converter
I/O PORT 5
( SPI )
8
6
VSYNC
HSYNC
2
Note : 42 SDIP shown
PLLR
PLLF
VR01995E
Note 1.
EPROM version only
3/20
®
ST9291
GENERAL DESCRIPTION
(Continued)
The control of TV or Satellite receiver setting can
be done by up to eight 8-bit PWM outputs, with a
frequency maximum of 23,437Hz at 8-bit resolu-
tion (INTCLK = 12MHz). Low resolutions with
higher frequency operation can be programmed.
In addition thereis a 3 channelAnalog to Digital Con-
verter with integral sample and hold, fast 5.75µs con-
version time and 6-bit guaranteedresolution.
PIN DESCRIPTION
VSYNC.
Vertical Sync.
Vertical video synchronisa-
tion input to OSD. Positive or negative polarity.
HSYNC.
Horizontal Sync.
Horizontal video syn-
chronisation input to OSD. Positive or negative po-
larity.
PLLF.
PLL Filter input.
Filter input for the OSD for
PLL feed-back.
PLLR.
PLL Resistor connection pin.
For resistor
connection to select the PLL gain adjust.
RESET.
Reset (input, active low).
The ST9 is initial-
ised by the Reset signal. With the deactivationof RE-
SET, program execution begins from the Program
memory location pointed to by the vector contained
in program memory locations 00h and 01h.
OSCIN, OSCOUT.
Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the in-
put of the oscillator inverter and internal clock gen-
erator; OSCOUT is the output of the oscillator
inverter.
AV
DD
. Analog V
DD
of PLL. This pin must be tied to
V
DD
externally to the ST9291.
V
DD
. Main Power Supply Voltage (5V±10%)
V
SS
. Digital Circuit Ground.
P0.0-P0.7, P2.0-P2.5, P3.0-P3.7, P4.0-P4.7,
P5.0-P5.1
(J suffix)
P0.0-P0.7, P1.0-P1.7, P2.0-P2.5, P3.0-P3.7,
P4.0-P4.7, P5.0-P5.3
(N suffix)
I/O Port Lines (In-
put/Output, TTL or CMOS compatible).
32/42 lines
grouped into I/O ports, bit programmable under
program control as general purpose I/O or as Alter-
nate functions (see next section).
P4.0 - P4.7 are high voltage (12V) open drain out-
puts. The voltage in open drain output mode for all
other I/O bits must not exceed V
DD
.
I/O Port Alternate Functions.
Each pin of the I/O ports of the ST9291 may as-
sume software programmable Alternative Func-
tions as shown in the Pin Configuration Drawings.
Table 1 shows the Functions allocated to each I/O
Port pin.
4/20
®
ST9291
PIN DESCRIPTION
(Continued)
Table 1.ST9291 I/O Port Alternative Function Summary
I/O PORT
Port.bit
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.1
P2.2
P2.2
P2.3
P2.3
P2.4
P2.5
P2.5
P3.0
P3.1
P3.2
P3.3
INT7
INT5
AIN1
INT0
AIN2
INT6
VSO1
NMI
AIN3
VSO2
FB
R
G
B
Name
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
O
I
I
O
O
O
O
O
External Interrupt 7 with Schmitt Trigger
External Interrupt 5 with Schmitt Trigger
A/D Analog Input 1
External Interrupt 0
A/D Analog Input 2
External Interrupt 6
Voltage Synthesis Output 1
Non-Maskable Interrupt
A/D Analog Input 3
Voltage Synthesis Output 2
Fast Blanking OSD output
Red Video Colour OSD output
Green Video Colour OSD output
Blue Video Colour OSD output
Alternate Function
Pin Assignment
9291J
10
9
8
7
6
5
4
3
-
-
-
-
-
-
-
-
1
42
42
41
41
40
40
39
38
38
18
17
16
15
9291N
12
11
10
9
8
6
5
4
52
51
50
49
48
47
46
45
2
1
1
56
56
55
55
54
53
53
23
22
21
20
5/20
®
FPGA/CPLD
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